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| author | Charlene Liu <charlene.liu@amd.com> | 2019-05-09 13:04:07 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:07 -0500 |
| commit | 8712bda45cdc9e40f92c5a513489a13de38cfdc0 (patch) | |
| tree | 677661f10da9423189943fb975688502d7229002 /tools/perf/scripts | |
| parent | 45021f8ea536b5d40decf35af6f91116dd112787 (diff) | |
| download | cachepc-linux-8712bda45cdc9e40f92c5a513489a13de38cfdc0.tar.gz cachepc-linux-8712bda45cdc9e40f92c5a513489a13de38cfdc0.zip | |
drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk.
[Description]
DMUB is using DPREF CLK, but DMCU still use displayclk.
This is for updating DMCU wait_for_loop after display clock change.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts')
0 files changed, 0 insertions, 0 deletions