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| author | Amelie Delaunay <amelie.delaunay@st.com> | 2018-04-19 15:21:42 +0200 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2018-05-06 22:22:42 +0200 |
| commit | deb7dcfbf00ccdf0d7fadfa4fa18adacef2b8b7a (patch) | |
| tree | a441b2fccf0babb1c94f9383f586c72c398c5b78 /tools/perf/scripts | |
| parent | d213217d213e0e5648448fc2a5da977a74dc6ad9 (diff) | |
| download | cachepc-linux-deb7dcfbf00ccdf0d7fadfa4fa18adacef2b8b7a.tar.gz cachepc-linux-deb7dcfbf00ccdf0d7fadfa4fa18adacef2b8b7a.zip | |
dt-bindings: rtc: update stm32-rtc documentation for st, syscfg property
RTC driver should not be aware of the PWR registers offset and bits
position. Furthermore, we can imagine that Disable Backup Protection (DBP)
relative register and bit mask could change depending on the SoC. So this
patch moves st,syscfg property from single pwrcfg phandle to pwrcfg
phandle/offset/mask triplet.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'tools/perf/scripts')
0 files changed, 0 insertions, 0 deletions