diff options
Diffstat (limited to 'include')
41 files changed, 787 insertions, 79 deletions
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h index edb0e2a602a8..ba1f860af38b 100644 --- a/include/asm-generic/bug.h +++ b/include/asm-generic/bug.h @@ -21,6 +21,12 @@ #include <linux/panic.h> #include <linux/printk.h> +struct warn_args; +struct pt_regs; + +void __warn(const char *file, int line, void *caller, unsigned taint, + struct pt_regs *regs, struct warn_args *args); + #ifdef CONFIG_BUG #ifdef CONFIG_GENERIC_BUG @@ -110,11 +116,6 @@ extern __printf(1, 2) void __warn_printk(const char *fmt, ...); #endif /* used internally by panic.c */ -struct warn_args; -struct pt_regs; - -void __warn(const char *file, int line, void *caller, unsigned taint, - struct pt_regs *regs, struct warn_args *args); #ifndef WARN_ON #define WARN_ON(condition) ({ \ diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 73f2a9324857..4048669bf756 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Daire McNamara,<daire.mcnamara@microchip.com> - * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ @@ -42,4 +42,7 @@ #define CLK_ATHENA 31 #define CLK_CFM 32 +#define CLK_RTCREF 33 +#define CLK_MSSPLL 34 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/memory/mt8186-memory-port.h b/include/dt-bindings/memory/mt8186-memory-port.h new file mode 100644 index 000000000000..2bc6e4433048 --- /dev/null +++ b/include/dt-bindings/memory/mt8186-memory-port.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * + * Author: Anan Sun <anan.sun@mediatek.com> + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +/* + * MM IOMMU supports 16GB dma address. We separate it to four ranges: + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters + * locate in anyone region. BUT: + * a) Make sure all the ports inside a larb are in one range. + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. + * + * This is the suggested mapping in this SoC: + * + * modules dma-address-region larbs-ports + * disp 0 ~ 4G larb0/1/2 + * vcodec 4G ~ 8G larb4/7 + * cam/mdp 8G ~ 12G the other larbs. + * N/A 12G ~ 16G + * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10 + * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5 + */ + +/* MM IOMMU ports */ +/* LARB 0 -- MMSYS */ +#define IOMMU_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) +#define IOMMU_PORT_L0_REVERSED MTK_M4U_ID(0, 1) +#define IOMMU_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) +#define IOMMU_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 3) + +/* LARB 1 -- MMSYS */ +#define IOMMU_PORT_L1_DISP_RDMA1 MTK_M4U_ID(1, 0) +#define IOMMU_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 1) +#define IOMMU_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 2) +#define IOMMU_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 3) +#define IOMMU_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 4) + +/* LARB 2 -- MMSYS */ +#define IOMMU_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) +#define IOMMU_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) +#define IOMMU_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) +#define IOMMU_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) +#define IOMMU_PORT_L2_DISP_FAKE0 MTK_M4U_ID(2, 4) + +/* LARB 4 -- VDEC */ +#define IOMMU_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_ID(4, 0) +#define IOMMU_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_ID(4, 1) +#define IOMMU_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_ID(4, 2) +#define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) +#define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) +#define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) +#define IOMMU_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_ID(4, 6) +#define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7) +#define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) +#define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) +#define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10) +#define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11) +#define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_ID(4, 12) +#define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_ID(4, 13) + +/* LARB 7 -- VENC */ +#define IOMMU_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) +#define IOMMU_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) +#define IOMMU_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) +#define IOMMU_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) +#define IOMMU_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) +#define IOMMU_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) +#define IOMMU_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) +#define IOMMU_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) +#define IOMMU_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) +#define IOMMU_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) +#define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10) +#define IOMMU_PORT_L7_JPGENC_Q_TABLE MTK_M4U_ID(7, 11) +#define IOMMU_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) + +/* LARB 8 -- WPE */ +#define IOMMU_PORT_L8_WPE_RDMA_0 MTK_M4U_ID(8, 0) +#define IOMMU_PORT_L8_WPE_RDMA_1 MTK_M4U_ID(8, 1) +#define IOMMU_PORT_L8_WPE_WDMA_0 MTK_M4U_ID(8, 2) + +/* LARB 9 -- IMG-1 */ +#define IOMMU_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) +#define IOMMU_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) +#define IOMMU_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) +#define IOMMU_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) +#define IOMMU_PORT_L9_IMG_LCE_D1 MTK_M4U_ID(9, 4) +#define IOMMU_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) +#define IOMMU_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) +#define IOMMU_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) +#define IOMMU_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) +#define IOMMU_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) +#define IOMMU_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) +#define IOMMU_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) +#define IOMMU_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) +#define IOMMU_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) +#define IOMMU_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) +#define IOMMU_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_ID(9, 15) +#define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16) +#define IOMMU_PORT_L9_IMG_WPE_WDMA MTK_M4U_ID(9, 17) +#define IOMMU_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_ID(9, 18) +#define IOMMU_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_ID(9, 19) +#define IOMMU_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_ID(9, 20) +#define IOMMU_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_ID(9, 21) +#define IOMMU_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_ID(9, 22) +#define IOMMU_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_ID(9, 23) +#define IOMMU_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_ID(9, 24) +#define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25) +#define IOMMU_PORT_L9_IMG_RESERVE6 MTK_M4U_ID(9, 26) +#define IOMMU_PORT_L9_IMG_RESERVE7 MTK_M4U_ID(9, 27) +#define IOMMU_PORT_L9_IMG_RESERVE8 MTK_M4U_ID(9, 28) + +/* LARB 11 -- IMG-2 */ +#define IOMMU_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) +#define IOMMU_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) +#define IOMMU_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) +#define IOMMU_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) +#define IOMMU_PORT_L11_IMG_LCE_D1 MTK_M4U_ID(11, 4) +#define IOMMU_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) +#define IOMMU_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) +#define IOMMU_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) +#define IOMMU_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) +#define IOMMU_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) +#define IOMMU_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) +#define IOMMU_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) +#define IOMMU_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) +#define IOMMU_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) +#define IOMMU_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) +#define IOMMU_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) +#define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) +#define IOMMU_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) +#define IOMMU_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) +#define IOMMU_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) +#define IOMMU_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) +#define IOMMU_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) +#define IOMMU_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) +#define IOMMU_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) +#define IOMMU_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) +#define IOMMU_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) +#define IOMMU_PORT_L11_IMG_RESERVE6 MTK_M4U_ID(11, 26) +#define IOMMU_PORT_L11_IMG_RESERVE7 MTK_M4U_ID(11, 27) +#define IOMMU_PORT_L11_IMG_RESERVE8 MTK_M4U_ID(11, 28) + +/* LARB 13 -- CAM */ +#define IOMMU_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) +#define IOMMU_PORT_L13_CAM_MRAWO_0 MTK_M4U_ID(13, 1) +#define IOMMU_PORT_L13_CAM_MRAWO_1 MTK_M4U_ID(13, 2) +#define IOMMU_PORT_L13_CAM_CAMSV_4 MTK_M4U_ID(13, 6) +#define IOMMU_PORT_L13_CAM_CAMSV_5 MTK_M4U_ID(13, 7) +#define IOMMU_PORT_L13_CAM_CAMSV_6 MTK_M4U_ID(13, 8) +#define IOMMU_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) +#define IOMMU_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) +#define IOMMU_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) + +/* LARB 14 -- CAM */ +#define IOMMU_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) +#define IOMMU_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) + +/* LARB 16 -- RAW-A */ +#define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) +#define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) +#define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) +#define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) +#define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) +#define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) +#define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) +#define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) +#define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) +#define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) +#define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) +#define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) +#define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) +#define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) +#define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) +#define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) +#define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) + +/* LARB 17 -- RAW-B */ +#define IOMMU_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) +#define IOMMU_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) +#define IOMMU_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) +#define IOMMU_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) +#define IOMMU_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) +#define IOMMU_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) +#define IOMMU_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) +#define IOMMU_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) +#define IOMMU_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) +#define IOMMU_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) +#define IOMMU_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) +#define IOMMU_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) +#define IOMMU_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) +#define IOMMU_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) +#define IOMMU_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) +#define IOMMU_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) +#define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) + +/* LARB 19 -- IPE */ +#define IOMMU_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) +#define IOMMU_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) +#define IOMMU_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) +#define IOMMU_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) + +/* LARB 20 -- IPE */ +#define IOMMU_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) +#define IOMMU_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) +#define IOMMU_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) +#define IOMMU_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) +#define IOMMU_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) +#define IOMMU_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) + +#endif diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h new file mode 100644 index 000000000000..70ba9f498eeb --- /dev/null +++ b/include/dt-bindings/memory/mt8195-memory-port.h @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +/* + * MM IOMMU supports 16GB dma address. We separate it to four ranges: + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters + * locate in anyone region. BUT: + * a) Make sure all the ports inside a larb are in one range. + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. + * + * This is the suggested mapping in this SoC: + * + * modules dma-address-region larbs-ports + * disp 0 ~ 4G larb0/1/2/3 + * vcodec 4G ~ 8G larb19/20/21/22/23/24 + * cam/mdp 8G ~ 12G the other larbs. + * N/A 12G ~ 16G + * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1 + * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3 + * + * This SoC have two IOMMU HWs, this is the detailed connected information: + * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28 + * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27 + */ + +/* MM IOMMU ports */ +/* larb0 */ +#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0) +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1) +#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2) +#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3) +#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4) +#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) + +/* larb1 */ +#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0) +#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1) +#define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2) +#define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3) +#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4) +#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5) + +/* larb2 */ +#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) +#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1) +#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2) +#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3) +#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4) + +/* larb3 */ +#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0) +#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1) +#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2) +#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3) +#define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4) +#define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5) +#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6) + +/* larb4 */ +#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0) +#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1) +#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2) +#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3) +#define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4) + +/* larb5 */ +#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0) +#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1) +#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2) +#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3) +#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4) +#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5) +#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6) +#define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7) + +/* larb6 */ +#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0) +#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1) +#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2) +#define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3) + +/* larb7 */ +#define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0) +#define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1) +#define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2) + +/* larb8 */ +#define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0) +#define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1) +#define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2) + +/* larb9 */ +#define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0) +#define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1) +#define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2) +#define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3) +#define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4) +#define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5) +#define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6) +#define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7) +#define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8) +#define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9) +#define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10) +#define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11) +#define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12) +#define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13) +#define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14) +#define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15) +#define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16) +#define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17) +#define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18) +#define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19) + +/* larb10 */ +#define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0) +#define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1) +#define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2) +#define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3) +#define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4) +#define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5) +#define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6) +#define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7) +#define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8) +#define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9) +#define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10) +#define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11) +#define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12) +#define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13) +#define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14) +#define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15) +#define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16) +#define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17) +#define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18) +#define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19) +#define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20) +#define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21) +#define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22) +#define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23) + +/* larb11 */ +#define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0) +#define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1) +#define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2) +#define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3) +#define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4) +#define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5) +#define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6) +#define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7) +#define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8) +#define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9) + +/* larb12 */ +#define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0) +#define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1) +#define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2) +#define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3) +#define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4) +#define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5) +#define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6) +#define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7) +#define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8) +#define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9) + +/* larb13 */ +#define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0) +#define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1) +#define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2) +#define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3) +#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4) +#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5) +#define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6) +#define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7) +#define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8) +#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9) + +/* larb14 */ +#define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0) +#define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1) +#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2) +#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3) +#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4) +#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5) +#define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6) +#define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7) +#define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8) +#define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9) +#define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10) +#define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11) +#define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12) +#define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13) +#define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14) + +/* larb15: null */ + +/* larb16 */ +#define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0) +#define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1) +#define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2) +#define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3) +#define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4) +#define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5) +#define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6) +#define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7) +#define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8) +#define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9) +#define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10) +#define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11) +#define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12) +#define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13) +#define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14) +#define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15) + +/* larb17 */ +#define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0) +#define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1) +#define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2) +#define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3) +#define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4) +#define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5) +#define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6) + +/* larb18 */ +#define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0) +#define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1) +#define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2) +#define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3) + +/* larb19 */ +#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0) +#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1) +#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2) +#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3) +#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4) +#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5) +#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6) +#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7) +#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8) +#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9) +#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10) +#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11) +#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12) +#define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13) +#define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14) +#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15) +#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16) +#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17) +#define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18) +#define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19) +#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20) +#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21) +#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22) +#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23) +#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24) +#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25) +#define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26) + +/* larb20 */ +#define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0) +#define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1) +#define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2) +#define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3) +#define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4) +#define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5) +#define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6) +#define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7) +#define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8) +#define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9) +#define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10) +#define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11) +#define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12) +#define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13) +#define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14) +#define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15) +#define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16) +#define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17) +#define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18) +#define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19) +#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20) +#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21) +#define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22) +#define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23) +#define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24) +#define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25) +#define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26) + +/* larb21 */ +#define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0) +#define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1) +#define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2) +#define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3) +#define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4) +#define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5) +#define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6) +#define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7) +#define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8) +#define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9) + +/* larb22 */ +#define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0) +#define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1) +#define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2) +#define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3) +#define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4) +#define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5) +#define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6) +#define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7) +#define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8) +#define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9) + +/* larb23 */ +#define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0) +#define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1) + +/* larb24 */ +#define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0) +#define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1) +#define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2) +#define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3) +#define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4) +#define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5) +#define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6) +#define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7) +#define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8) +#define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9) +#define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10) +#define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11) + +/* larb25 */ +#define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0) +#define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1) +#define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2) +#define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3) +#define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4) +#define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5) +#define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6) +#define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7) +#define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8) +#define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9) +#define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10) +#define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11) + +/* larb26 */ +#define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0) +#define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1) +#define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2) +#define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3) +#define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4) +#define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5) +#define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6) +#define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7) +#define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8) +#define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9) +#define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10) +#define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11) + +/* larb27 */ +#define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0) +#define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1) +#define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2) +#define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3) +#define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4) +#define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5) +#define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6) +#define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7) +#define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8) +#define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9) +#define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10) +#define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11) +#define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12) +#define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13) +#define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14) +#define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15) + +/* larb28 */ +#define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0) +#define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1) +#define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2) +#define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3) +#define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4) +#define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5) +#define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6) + +/* Infra iommu ports */ +/* PCIe1: read: BIT16; write BIT17. */ +#define IOMMU_PORT_INFRA_PCIE1 MTK_IFAIOMMU_PERI_ID(16) +/* PCIe0: read: BIT18; write BIT19. */ +#define IOMMU_PORT_INFRA_PCIE0 MTK_IFAIOMMU_PERI_ID(18) +#define IOMMU_PORT_INFRA_SSUSB_P3_R MTK_IFAIOMMU_PERI_ID(20) +#define IOMMU_PORT_INFRA_SSUSB_P3_W MTK_IFAIOMMU_PERI_ID(21) +#define IOMMU_PORT_INFRA_SSUSB_P2_R MTK_IFAIOMMU_PERI_ID(22) +#define IOMMU_PORT_INFRA_SSUSB_P2_W MTK_IFAIOMMU_PERI_ID(23) +#define IOMMU_PORT_INFRA_SSUSB_P1_1_R MTK_IFAIOMMU_PERI_ID(24) +#define IOMMU_PORT_INFRA_SSUSB_P1_1_W MTK_IFAIOMMU_PERI_ID(25) +#define IOMMU_PORT_INFRA_SSUSB_P1_0_R MTK_IFAIOMMU_PERI_ID(26) +#define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27) +#define IOMMU_PORT_INFRA_SSUSB2_R MTK_IFAIOMMU_PERI_ID(28) +#define IOMMU_PORT_INFRA_SSUSB2_W MTK_IFAIOMMU_PERI_ID(29) +#define IOMMU_PORT_INFRA_SSUSB_R MTK_IFAIOMMU_PERI_ID(30) +#define IOMMU_PORT_INFRA_SSUSB_W MTK_IFAIOMMU_PERI_ID(31) + +#endif diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h index 7d64103209af..2f68a0511a25 100644 --- a/include/dt-bindings/memory/mtk-memory-port.h +++ b/include/dt-bindings/memory/mtk-memory-port.h @@ -12,4 +12,6 @@ #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) +#define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port) + #endif diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index 6562f543c3e0..2ddce9bcd00e 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -79,6 +79,14 @@ struct amba_driver { void (*remove)(struct amba_device *); void (*shutdown)(struct amba_device *); const struct amba_id *id_table; + /* + * For most device drivers, no need to care about this flag as long as + * all DMAs are handled through the kernel DMA API. For some special + * ones, for example VFIO drivers, they know how to manage the DMA + * themselves and set this flag so that the IOMMU layer will allow them + * to setup and manage their own I/O address space. + */ + bool driver_managed_dma; }; /* diff --git a/include/linux/bio.h b/include/linux/bio.h index 278cc81cc1e7..00450fd86bb4 100644 --- a/include/linux/bio.h +++ b/include/linux/bio.h @@ -269,6 +269,7 @@ struct folio_iter { size_t offset; size_t length; /* private: for use by the iterator */ + struct folio *_next; size_t _seg_count; int _i; }; @@ -283,6 +284,7 @@ static inline void bio_first_folio(struct folio_iter *fi, struct bio *bio, PAGE_SIZE * (bvec->bv_page - &fi->folio->page); fi->_seg_count = bvec->bv_len; fi->length = min(folio_size(fi->folio) - fi->offset, fi->_seg_count); + fi->_next = folio_next(fi->folio); fi->_i = i; } @@ -290,9 +292,10 @@ static inline void bio_next_folio(struct folio_iter *fi, struct bio *bio) { fi->_seg_count -= fi->length; if (fi->_seg_count) { - fi->folio = folio_next(fi->folio); + fi->folio = fi->_next; fi->offset = 0; fi->length = min(folio_size(fi->folio), fi->_seg_count); + fi->_next = folio_next(fi->folio); } else if (fi->_i + 1 < bio->bi_vcnt) { bio_first_folio(fi, bio, fi->_i + 1); } else { diff --git a/include/linux/blk-mq.h b/include/linux/blk-mq.h index 7aa5c54901a9..9f07061418db 100644 --- a/include/linux/blk-mq.h +++ b/include/linux/blk-mq.h @@ -163,7 +163,6 @@ struct request { struct rb_node rb_node; /* sort/lookup */ struct bio_vec special_vec; void *completion_data; - int error_count; /* for legacy drivers, don't use */ }; diff --git a/include/linux/cpu.h b/include/linux/cpu.h index 9cf51e41e697..54dc2f9a2d56 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -167,7 +167,7 @@ static inline int suspend_disable_secondary_cpus(void) { return 0; } static inline void suspend_enable_secondary_cpus(void) { } #endif /* !CONFIG_PM_SLEEP_SMP */ -void cpu_startup_entry(enum cpuhp_state state); +void __noreturn cpu_startup_entry(enum cpuhp_state state); void cpu_idle_poll_ctrl(bool enable); diff --git a/include/linux/device/bus.h b/include/linux/device/bus.h index a039ab809753..d8b29ccd07e5 100644 --- a/include/linux/device/bus.h +++ b/include/linux/device/bus.h @@ -59,6 +59,8 @@ struct fwnode_handle; * bus supports. * @dma_configure: Called to setup DMA configuration on a device on * this bus. + * @dma_cleanup: Called to cleanup DMA configuration on a device on + * this bus. * @pm: Power management operations of this bus, callback the specific * device driver's pm-ops. * @iommu_ops: IOMMU specific operations for this bus, used to attach IOMMU @@ -103,6 +105,7 @@ struct bus_type { int (*num_vf)(struct device *dev); int (*dma_configure)(struct device *dev); + void (*dma_cleanup)(struct device *dev); const struct dev_pm_ops *pm; diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h index 7b6c42bfb660..27efef8affb1 100644 --- a/include/linux/fsl/mc.h +++ b/include/linux/fsl/mc.h @@ -32,6 +32,13 @@ struct fsl_mc_io; * @shutdown: Function called at shutdown time to quiesce the device * @suspend: Function called when a device is stopped * @resume: Function called when a device is resumed + * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. + * For most device drivers, no need to care about this flag + * as long as all DMAs are handled through the kernel DMA API. + * For some special ones, for example VFIO drivers, they know + * how to manage the DMA themselves and set this flag so that + * the IOMMU layer will allow them to setup and manage their + * own I/O address space. * * Generic DPAA device driver object for device drivers that are registered * with a DPRC bus. This structure is to be embedded in each device-specific @@ -45,6 +52,7 @@ struct fsl_mc_driver { void (*shutdown)(struct fsl_mc_device *dev); int (*suspend)(struct fsl_mc_device *dev, pm_message_t state); int (*resume)(struct fsl_mc_device *dev); + bool driver_managed_dma; }; #define to_fsl_mc_driver(_drv) \ diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 2f9891cb3d00..4f29139bbfc3 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -539,7 +539,8 @@ struct dmar_domain { u8 has_iotlb_device: 1; u8 iommu_coherency: 1; /* indicate coherency of iommu access */ - u8 iommu_snooping: 1; /* indicate snooping control feature */ + u8 force_snooping : 1; /* Create IOPTEs with snoop control */ + u8 set_pte_snp:1; struct list_head devices; /* all devices' list */ struct iova_domain iovad; /* iova's that belong to this domain */ diff --git a/include/linux/intel-svm.h b/include/linux/intel-svm.h index b3b125b332aa..207ef06ba3e1 100644 --- a/include/linux/intel-svm.h +++ b/include/linux/intel-svm.h @@ -9,7 +9,7 @@ #define __INTEL_SVM_H__ /* Page Request Queue depth */ -#define PRQ_ORDER 2 +#define PRQ_ORDER 4 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20) #define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 9208eca4b0d1..5e1afe169549 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -103,10 +103,11 @@ static inline bool iommu_is_dma_domain(struct iommu_domain *domain) } enum iommu_cap { - IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA - transactions */ + IOMMU_CAP_CACHE_COHERENCY, /* IOMMU_CACHE is supported */ IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */ IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ + IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for + DMA protection and we should too */ }; /* These are the possible reserved region types */ @@ -272,6 +273,9 @@ struct iommu_ops { * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush * queue * @iova_to_phys: translate iova to physical address + * @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE, + * including no-snoop TLPs on PCIe or other platform + * specific mechanisms. * @enable_nesting: Enable nesting * @set_pgtable_quirks: Set io page table quirks (IO_PGTABLE_QUIRK_*) * @free: Release the domain after use. @@ -300,6 +304,7 @@ struct iommu_domain_ops { phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); + bool (*enforce_cache_coherency)(struct iommu_domain *domain); int (*enable_nesting)(struct iommu_domain *domain); int (*set_pgtable_quirks)(struct iommu_domain *domain, unsigned long quirks); @@ -407,16 +412,10 @@ static inline const struct iommu_ops *dev_iommu_ops(struct device *dev) return dev->iommu->iommu_dev->ops; } -#define IOMMU_GROUP_NOTIFY_ADD_DEVICE 1 /* Device added */ -#define IOMMU_GROUP_NOTIFY_DEL_DEVICE 2 /* Pre Device removed */ -#define IOMMU_GROUP_NOTIFY_BIND_DRIVER 3 /* Pre Driver bind */ -#define IOMMU_GROUP_NOTIFY_BOUND_DRIVER 4 /* Post Driver bind */ -#define IOMMU_GROUP_NOTIFY_UNBIND_DRIVER 5 /* Pre Driver unbind */ -#define IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER 6 /* Post Driver unbind */ - extern int bus_set_iommu(struct bus_type *bus, const struct iommu_ops *ops); extern int bus_iommu_probe(struct bus_type *bus); extern bool iommu_present(struct bus_type *bus); +extern bool device_iommu_capable(struct device *dev, enum iommu_cap cap); extern bool iommu_capable(struct bus_type *bus, enum iommu_cap cap); extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus); extern struct iommu_group *iommu_group_get_by_id(int id); @@ -478,10 +477,6 @@ extern int iommu_group_for_each_dev(struct iommu_group *group, void *data, extern struct iommu_group *iommu_group_get(struct device *dev); extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group); extern void iommu_group_put(struct iommu_group *group); -extern int iommu_group_register_notifier(struct iommu_group *group, - struct notifier_block *nb); -extern int iommu_group_unregister_notifier(struct iommu_group *group, - struct notifier_block *nb); extern int iommu_register_device_fault_handler(struct device *dev, iommu_dev_fault_handler_t handler, void *data); @@ -675,6 +670,13 @@ struct iommu_sva *iommu_sva_bind_device(struct device *dev, void iommu_sva_unbind_device(struct iommu_sva *handle); u32 iommu_sva_get_pasid(struct iommu_sva *handle); +int iommu_device_use_default_domain(struct device *dev); +void iommu_device_unuse_default_domain(struct device *dev); + +int iommu_group_claim_dma_owner(struct iommu_group *group, void *owner); +void iommu_group_release_dma_owner(struct iommu_group *group); +bool iommu_group_dma_owner_claimed(struct iommu_group *group); + #else /* CONFIG_IOMMU_API */ struct iommu_ops {}; @@ -689,6 +691,11 @@ static inline bool iommu_present(struct bus_type *bus) return false; } +static inline bool device_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + return false; +} + static inline bool iommu_capable(struct bus_type *bus, enum iommu_cap cap) { return false; @@ -871,18 +878,6 @@ static inline void iommu_group_put(struct iommu_group *group) { } -static inline int iommu_group_register_notifier(struct iommu_group *group, - struct notifier_block *nb) -{ - return -ENODEV; -} - -static inline int iommu_group_unregister_notifier(struct iommu_group *group, - struct notifier_block *nb) -{ - return 0; -} - static inline int iommu_register_device_fault_handler(struct device *dev, iommu_dev_fault_handler_t handler, @@ -1031,6 +1026,30 @@ static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) { return NULL; } + +static inline int iommu_device_use_default_domain(struct device *dev) +{ + return 0; +} + +static inline void iommu_device_unuse_default_domain(struct device *dev) +{ +} + +static inline int +iommu_group_claim_dma_owner(struct iommu_group *group, void *owner) +{ + return -ENODEV; +} + +static inline void iommu_group_release_dma_owner(struct iommu_group *group) +{ +} + +static inline bool iommu_group_dma_owner_claimed(struct iommu_group *group) +{ + return false; +} #endif /* CONFIG_IOMMU_API */ /** diff --git a/include/linux/kernel.h b/include/linux/kernel.h index a890428bcc1a..fe6efb24d151 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -285,7 +285,7 @@ static inline char *hex_byte_pack_upper(char *buf, u8 byte) return buf; } -extern int hex_to_bin(char ch); +extern int hex_to_bin(unsigned char ch); extern int __must_check hex2bin(u8 *dst, const char *src, size_t count); extern char *bin2hex(char *dst, const void *src, size_t count); diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 151607e9d64a..955aee14b0f7 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -389,10 +389,8 @@ struct mtd_info { /* List of partitions attached to this MTD device */ struct list_head partitions; - union { - struct mtd_part part; - struct mtd_master master; - }; + struct mtd_part part; + struct mtd_master master; }; static inline struct mtd_info *mtd_get_master(struct mtd_info *mtd) diff --git a/include/linux/netdev_features.h b/include/linux/netdev_features.h index 2c6b9e416225..7c2d77d75a88 100644 --- a/include/linux/netdev_features.h +++ b/include/linux/netdev_features.h @@ -169,7 +169,7 @@ enum { #define NETIF_F_HW_HSR_FWD __NETIF_F(HW_HSR_FWD) #define NETIF_F_HW_HSR_DUP __NETIF_F(HW_HSR_DUP) -/* Finds the next feature with the highest number of the range of start till 0. +/* Finds the next feature with the highest number of the range of start-1 till 0. */ static inline int find_next_netdev_feature(u64 feature, unsigned long start) { @@ -188,7 +188,7 @@ static inline int find_next_netdev_feature(u64 feature, unsigned long start) for ((bit) = find_next_netdev_feature((mask_addr), \ NETDEV_FEATURE_COUNT); \ (bit) >= 0; \ - (bit) = find_next_netdev_feature((mask_addr), (bit) - 1)) + (bit) = find_next_netdev_feature((mask_addr), (bit))) /* Features valid for ethtool to change */ /* = all defined minus driver/device-class-related */ diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 59e27a2b7bf0..b1fbe21650bb 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -199,10 +199,10 @@ struct net_device_stats { * Try to fit them in a single cache line, for dev_get_stats() sake. */ struct net_device_core_stats { - local_t rx_dropped; - local_t tx_dropped; - local_t rx_nohandler; -} __aligned(4 * sizeof(local_t)); + unsigned long rx_dropped; + unsigned long tx_dropped; + unsigned long rx_nohandler; +} __aligned(4 * sizeof(unsigned long)); #include <linux/cache.h> #include <linux/skbuff.h> @@ -3843,15 +3843,15 @@ static __always_inline bool __is_skb_forwardable(const struct net_device *dev, return false; } -struct net_device_core_stats *netdev_core_stats_alloc(struct net_device *dev); +struct net_device_core_stats __percpu *netdev_core_stats_alloc(struct net_device *dev); -static inline struct net_device_core_stats *dev_core_stats(struct net_device *dev) +static inline struct net_device_core_stats __percpu *dev_core_stats(struct net_device *dev) { /* This READ_ONCE() pairs with the write in netdev_core_stats_alloc() */ struct net_device_core_stats __percpu *p = READ_ONCE(dev->core_stats); if (likely(p)) - return this_cpu_ptr(p); + return p; return netdev_core_stats_alloc(dev); } @@ -3859,14 +3859,11 @@ static inline struct net_device_core_stats *dev_core_stats(struct net_device *de #define DEV_CORE_STATS_INC(FIELD) \ static inline void dev_core_stats_##FIELD##_inc(struct net_device *dev) \ { \ - struct net_device_core_stats *p; \ + struct net_device_core_stats __percpu *p; \ \ - preempt_disable(); \ p = dev_core_stats(dev); \ - \ if (p) \ - local_inc(&p->FIELD); \ - preempt_enable(); \ + this_cpu_inc(p->FIELD); \ } DEV_CORE_STATS_INC(rx_dropped) DEV_CORE_STATS_INC(tx_dropped) diff --git a/include/linux/pci.h b/include/linux/pci.h index 60adf42460ab..b933d2b08d4d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -895,6 +895,13 @@ struct module; * created once it is bound to the driver. * @driver: Driver model structure. * @dynids: List of dynamically added device IDs. + * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. + * For most device drivers, no need to care about this flag + * as long as all DMAs are handled through the kernel DMA API. + * For some special ones, for example VFIO drivers, they know + * how to manage the DMA themselves and set this flag so that + * the IOMMU layer will allow them to setup and manage their + * own I/O address space. */ struct pci_driver { struct list_head node; @@ -913,6 +920,7 @@ struct pci_driver { const struct attribute_group **dev_groups; struct device_driver driver; struct pci_dynids dynids; + bool driver_managed_dma; }; static inline struct pci_driver *to_pci_driver(struct device_driver *drv) diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 7c96f169d274..b3d9c744f1e5 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -210,6 +210,14 @@ struct platform_driver { struct device_driver driver; const struct platform_device_id *id_table; bool prevent_deferred_probe; + /* + * For most device drivers, no need to care about this flag as long as + * all DMAs are handled through the kernel DMA API. For some special + * ones, for example VFIO drivers, they know how to manage the DMA + * themselves and set this flag so that the IOMMU layer will allow them + * to setup and manage their own I/O address space. + */ + bool driver_managed_dma; }; #define to_platform_driver(drv) (container_of((drv), struct platform_driver, \ @@ -328,8 +336,6 @@ extern int platform_pm_restore(struct device *dev); #define platform_pm_restore NULL #endif -extern int platform_dma_configure(struct device *dev); - #ifdef CONFIG_PM_SLEEP #define USE_PLATFORM_PM_SLEEP_OPS \ .suspend = platform_pm_suspend, \ diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 24eea1b05ca2..29917850f079 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -270,5 +270,6 @@ struct plat_stmmacenet_data { int msi_rx_base_vec; int msi_tx_base_vec; bool use_phy_wol; + bool sph_disable; }; #endif diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 267b7aeaf1a6..90501404fa49 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -160,6 +160,7 @@ struct rpc_add_xprt_test { #define RPC_CLNT_CREATE_NO_RETRANS_TIMEOUT (1UL << 9) #define RPC_CLNT_CREATE_SOFTERR (1UL << 10) #define RPC_CLNT_CREATE_REUSEPORT (1UL << 11) +#define RPC_CLNT_CREATE_CONNECTED (1UL << 12) struct rpc_clnt *rpc_create(struct rpc_create_args *args); struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *, diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index 124e13cb1469..7a8ad984e651 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -465,6 +465,7 @@ static inline struct tb_xdomain *tb_service_parent(struct tb_service *svc) * @msix_ida: Used to allocate MSI-X vectors for rings * @going_away: The host controller device is about to disappear so when * this flag is set, avoid touching the hardware anymore. + * @iommu_dma_protection: An IOMMU will isolate external-facing ports. * @interrupt_work: Work scheduled to handle ring interrupt when no * MSI-X is used. * @hop_count: Number of rings (end point hops) supported by NHI. @@ -479,6 +480,7 @@ struct tb_nhi { struct tb_ring **rx_rings; struct ida msix_ida; bool going_away; + bool iommu_dma_protection; struct work_struct interrupt_work; u32 hop_count; unsigned long quirks; diff --git a/include/linux/usb/pd_bdo.h b/include/linux/usb/pd_bdo.h index 033fe3e17141..7c25b88d79f9 100644 --- a/include/linux/usb/pd_bdo.h +++ b/include/linux/usb/pd_bdo.h @@ -15,7 +15,7 @@ #define BDO_MODE_CARRIER2 (5 << 28) #define BDO_MODE_CARRIER3 (6 << 28) #define BDO_MODE_EYE (7 << 28) -#define BDO_MODE_TESTDATA (8 << 28) +#define BDO_MODE_TESTDATA (8U << 28) #define BDO_MODE_MASK(mode) ((mode) & 0xf0000000) diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 7c93f5177532..9c0ad64b8d29 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -72,6 +72,7 @@ struct rpcif { enum rpcif_type type; enum rpcif_data_dir dir; u8 bus_size; + u8 xfer_size; void *buffer; u32 xferlen; u32 smcr; diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h index 5cb095b09a94..69ef31cea582 100644 --- a/include/net/bluetooth/hci.h +++ b/include/net/bluetooth/hci.h @@ -578,6 +578,7 @@ enum { #define HCI_ERROR_CONNECTION_TIMEOUT 0x08 #define HCI_ERROR_REJ_LIMITED_RESOURCES 0x0d #define HCI_ERROR_REJ_BAD_ADDR 0x0f +#define HCI_ERROR_INVALID_PARAMETERS 0x12 #define HCI_ERROR_REMOTE_USER_TERM 0x13 #define HCI_ERROR_REMOTE_LOW_RESOURCES 0x14 #define HCI_ERROR_REMOTE_POWER_OFF 0x15 diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index d5377740e99c..62d7b81b1cb7 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -36,6 +36,9 @@ /* HCI priority */ #define HCI_PRIO_MAX 7 +/* HCI maximum id value */ +#define HCI_MAX_ID 10000 + /* HCI Core structures */ struct inquiry_data { bdaddr_t bdaddr; @@ -1156,7 +1159,7 @@ int hci_conn_switch_role(struct hci_conn *conn, __u8 role); void hci_conn_enter_active_mode(struct hci_conn *conn, __u8 force_active); -void hci_le_conn_failed(struct hci_conn *conn, u8 status); +void hci_conn_failed(struct hci_conn *conn, u8 status); /* * hci_conn_get() and hci_conn_put() are used to control the life-time of an diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h index f72ec113ae56..98e1ec1a14f0 100644 --- a/include/net/inet_hashtables.h +++ b/include/net/inet_hashtables.h @@ -425,7 +425,7 @@ static inline void sk_rcv_saddr_set(struct sock *sk, __be32 addr) } int __inet_hash_connect(struct inet_timewait_death_row *death_row, - struct sock *sk, u32 port_offset, + struct sock *sk, u64 port_offset, int (*check_established)(struct inet_timewait_death_row *, struct sock *, __u16, struct inet_timewait_sock **)); diff --git a/include/net/ip6_tunnel.h b/include/net/ip6_tunnel.h index a38c4f1e4e5c..74b369bddf49 100644 --- a/include/net/ip6_tunnel.h +++ b/include/net/ip6_tunnel.h @@ -58,7 +58,7 @@ struct ip6_tnl { /* These fields used only by GRE */ __u32 i_seqno; /* The last seen seqno */ - __u32 o_seqno; /* The last output seqno */ + atomic_t o_seqno; /* The last output seqno */ int hlen; /* tun_hlen + encap_hlen */ int tun_hlen; /* Precalculated header length */ int encap_hlen; /* Encap header length (FOU,GUE) */ diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h index 88dee57eac8a..c24fa934221d 100644 --- a/include/net/ip_tunnels.h +++ b/include/net/ip_tunnels.h @@ -116,7 +116,7 @@ struct ip_tunnel { /* These four fields used only by GRE */ u32 i_seqno; /* The last seen seqno */ - u32 o_seqno; /* The last output seqno */ + atomic_t o_seqno; /* The last output seqno */ int tun_hlen; /* Precalculated header length */ /* These four fields used only by ERSPAN */ diff --git a/include/net/secure_seq.h b/include/net/secure_seq.h index d7d2495f83c2..dac91aa38c5a 100644 --- a/include/net/secure_seq.h +++ b/include/net/secure_seq.h @@ -4,8 +4,8 @@ #include <linux/types.h> -u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); -u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, +u64 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); +u64 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, __be16 dport); u32 secure_tcp_seq(__be32 saddr, __be32 daddr, __be16 sport, __be16 dport); diff --git a/include/net/tc_act/tc_pedit.h b/include/net/tc_act/tc_pedit.h index 748cf87a4d7e..3e02709a1df6 100644 --- a/include/net/tc_act/tc_pedit.h +++ b/include/net/tc_act/tc_pedit.h @@ -14,6 +14,7 @@ struct tcf_pedit { struct tc_action common; unsigned char tcfp_nkeys; unsigned char tcfp_flags; + u32 tcfp_off_max_hint; struct tc_pedit_key *tcfp_keys; struct tcf_pedit_key_ex *tcfp_keys_ex; }; diff --git a/include/net/tcp.h b/include/net/tcp.h index 70ca4a5e330a..cc1295037533 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -480,6 +480,7 @@ int __cookie_v4_check(const struct iphdr *iph, const struct tcphdr *th, u32 cookie); struct sock *cookie_v4_check(struct sock *sk, struct sk_buff *skb); struct request_sock *cookie_tcp_reqsk_alloc(const struct request_sock_ops *ops, + const struct tcp_request_sock_ops *af_ops, struct sock *sk, struct sk_buff *skb); #ifdef CONFIG_SYN_COOKIES @@ -620,6 +621,7 @@ void tcp_synack_rtt_meas(struct sock *sk, struct request_sock *req); void tcp_reset(struct sock *sk, struct sk_buff *skb); void tcp_skb_mark_lost_uncond_verify(struct tcp_sock *tp, struct sk_buff *skb); void tcp_fin(struct sock *sk); +void tcp_check_space(struct sock *sk); /* tcp_timer.c */ void tcp_init_xmit_timers(struct sock *); @@ -1042,6 +1044,7 @@ struct rate_sample { int losses; /* number of packets marked lost upon ACK */ u32 acked_sacked; /* number of packets newly (S)ACKed upon ACK */ u32 prior_in_flight; /* in flight before this ACK */ + u32 last_end_seq; /* end_seq of most recently ACKed packet */ bool is_app_limited; /* is sample from packet with bubble in pipe? */ bool is_retrans; /* is sample from retransmission? */ bool is_ack_delayed; /* is this (likely) a delayed ACK? */ @@ -1164,6 +1167,11 @@ void tcp_rate_gen(struct sock *sk, u32 delivered, u32 lost, bool is_sack_reneg, struct rate_sample *rs); void tcp_rate_check_app_limited(struct sock *sk); +static inline bool tcp_skb_sent_after(u64 t1, u64 t2, u32 seq1, u32 seq2) +{ + return t1 > t2 || (t1 == t2 && after(seq1, seq2)); +} + /* These functions determine how the current flow behaves in respect of SACK * handling. SACK is negotiated with the peer, and therefore it can vary * between different flows. diff --git a/include/net/xsk_buff_pool.h b/include/net/xsk_buff_pool.h index 5554ee75e7da..647722e847b4 100644 --- a/include/net/xsk_buff_pool.h +++ b/include/net/xsk_buff_pool.h @@ -97,6 +97,7 @@ int xp_assign_dev(struct xsk_buff_pool *pool, struct net_device *dev, u16 queue_id, u16 flags); int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_umem *umem, struct net_device *dev, u16 queue_id); +int xp_alloc_tx_descs(struct xsk_buff_pool *pool, struct xdp_sock *xs); void xp_destroy(struct xsk_buff_pool *pool); void xp_get_pool(struct xsk_buff_pool *pool); bool xp_put_pool(struct xsk_buff_pool *pool); diff --git a/include/soc/mscc/ocelot_vcap.h b/include/soc/mscc/ocelot_vcap.h index 7b2bf9b1fe69..de26c992f821 100644 --- a/include/soc/mscc/ocelot_vcap.h +++ b/include/soc/mscc/ocelot_vcap.h @@ -681,7 +681,6 @@ struct ocelot_vcap_id { struct ocelot_vcap_filter { struct list_head list; - struct list_head trap_list; enum ocelot_vcap_filter_type type; int block_id; @@ -695,6 +694,7 @@ struct ocelot_vcap_filter { struct ocelot_vcap_stats stats; /* For VCAP IS1 and IS2 */ bool take_ts; + bool is_trap; unsigned long ingress_port_mask; /* For VCAP ES0 */ struct ocelot_vcap_port ingress_port; diff --git a/include/trace/events/sched.h b/include/trace/events/sched.h index 65e786756321..fbb99a61f714 100644 --- a/include/trace/events/sched.h +++ b/include/trace/events/sched.h @@ -222,11 +222,11 @@ static inline long __trace_sched_switch_state(bool preempt, TRACE_EVENT(sched_switch, TP_PROTO(bool preempt, - unsigned int prev_state, struct task_struct *prev, - struct task_struct *next), + struct task_struct *next, + unsigned int prev_state), - TP_ARGS(preempt, prev_state, prev, next), + TP_ARGS(preempt, prev, next, prev_state), TP_STRUCT__entry( __array( char, prev_comm, TASK_COMM_LEN ) diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 787c657bfae8..7ce993e6786c 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -42,7 +42,7 @@ typedef __s64 Elf64_Sxword; /* ARM MTE memory tag segment type */ -#define PT_ARM_MEMTAG_MTE (PT_LOPROC + 0x1) +#define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2) /* * Extended Numbering diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h index 4c14e8be7267..3a49913d006c 100644 --- a/include/uapi/linux/fb.h +++ b/include/uapi/linux/fb.h @@ -182,7 +182,7 @@ struct fb_fix_screeninfo { * * For pseudocolor: offset and length should be the same for all color * components. Offset specifies the position of the least significant bit - * of the pallette index in a pixel value. Length indicates the number + * of the palette index in a pixel value. Length indicates the number * of available palette entries (i.e. # of entries = 1 << length). */ struct fb_bitfield { diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 91a6fe4e02c0..6a184d260c7f 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -445,7 +445,13 @@ struct kvm_run { #define KVM_SYSTEM_EVENT_RESET 2 #define KVM_SYSTEM_EVENT_CRASH 3 __u32 type; - __u64 flags; + __u32 ndata; + union { +#ifndef __KERNEL__ + __u64 flags; +#endif + __u64 data[16]; + }; } system_event; /* KVM_EXIT_S390_STSI */ struct { @@ -1144,6 +1150,8 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_S390_MEM_OP_EXTENSION 211 #define KVM_CAP_PMU_CAPABILITY 212 #define KVM_CAP_DISABLE_QUIRKS2 213 +/* #define KVM_CAP_VM_TSC_CONTROL 214 */ +#define KVM_CAP_SYSTEM_EVENT_DATA 215 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/include/uapi/linux/rfkill.h b/include/uapi/linux/rfkill.h index 283c5a7b3f2c..db6c8588c1d0 100644 --- a/include/uapi/linux/rfkill.h +++ b/include/uapi/linux/rfkill.h @@ -184,7 +184,7 @@ struct rfkill_event_ext { #define RFKILL_IOC_NOINPUT 1 #define RFKILL_IOCTL_NOINPUT _IO(RFKILL_IOC_MAGIC, RFKILL_IOC_NOINPUT) #define RFKILL_IOC_MAX_SIZE 2 -#define RFKILL_IOCTL_MAX_SIZE _IOW(RFKILL_IOC_MAGIC, RFKILL_IOC_EXT_SIZE, __u32) +#define RFKILL_IOCTL_MAX_SIZE _IOW(RFKILL_IOC_MAGIC, RFKILL_IOC_MAX_SIZE, __u32) /* and that's all userspace gets */ diff --git a/include/uapi/linux/virtio_ids.h b/include/uapi/linux/virtio_ids.h index 80d76b75bccd..7aa2eb766205 100644 --- a/include/uapi/linux/virtio_ids.h +++ b/include/uapi/linux/virtio_ids.h @@ -73,12 +73,12 @@ * Virtio Transitional IDs */ -#define VIRTIO_TRANS_ID_NET 1000 /* transitional virtio net */ -#define VIRTIO_TRANS_ID_BLOCK 1001 /* transitional virtio block */ -#define VIRTIO_TRANS_ID_BALLOON 1002 /* transitional virtio balloon */ -#define VIRTIO_TRANS_ID_CONSOLE 1003 /* transitional virtio console */ -#define VIRTIO_TRANS_ID_SCSI 1004 /* transitional virtio SCSI */ -#define VIRTIO_TRANS_ID_RNG 1005 /* transitional virtio rng */ -#define VIRTIO_TRANS_ID_9P 1009 /* transitional virtio 9p console */ +#define VIRTIO_TRANS_ID_NET 0x1000 /* transitional virtio net */ +#define VIRTIO_TRANS_ID_BLOCK 0x1001 /* transitional virtio block */ +#define VIRTIO_TRANS_ID_BALLOON 0x1002 /* transitional virtio balloon */ +#define VIRTIO_TRANS_ID_CONSOLE 0x1003 /* transitional virtio console */ +#define VIRTIO_TRANS_ID_SCSI 0x1004 /* transitional virtio SCSI */ +#define VIRTIO_TRANS_ID_RNG 0x1005 /* transitional virtio rng */ +#define VIRTIO_TRANS_ID_9P 0x1009 /* transitional virtio 9p console */ #endif /* _LINUX_VIRTIO_IDS_H */ |