| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | dt-bindings: bus: ti-sysc: Update to use yaml binding | Tony Lindgren | 2021-10-28 | 1 | -139/+0 |
| * | dt-bindings: bus: ti-sysc: Add support for PRUSS SYSC type | Roger Quadros | 2020-03-04 | 1 | -0/+1 |
| * | Documentation: bus: ti-sysc: fix spelling mistakes "multipe" and "interconnet" | Colin Ian King | 2019-04-05 | 1 | -2/+2 |
| * | bus: ti-sysc: Handle missed no-idle property in addition to no-idle-on-init | Tony Lindgren | 2019-04-01 | 1 | -0/+2 |
| * | bus: ti-sysc: Add mcasp optional clocks flag | Tony Lindgren | 2018-11-15 | 1 | -0/+1 |
| * | bus: ti-sysc: Add support for using ti-sysc for MCAN on dra76x | Faiz Abbas | 2018-07-09 | 1 | -0/+1 |
| * | bus: ti-sysc: Add handling for clkctrl opt clocks | Tony Lindgren | 2018-04-30 | 1 | -1/+5 |
| * | ARM: dts: Add generic ti,sysc compatible in addition to the custom ones | Tony Lindgren | 2017-12-21 | 1 | -0/+1 |
| * | dt-bindings: ti-sysc: Update binding for timers and capabilities | Tony Lindgren | 2017-12-15 | 1 | -0/+36 |
| * | dt-bindings: bus: Minimal TI sysc interconnect target module binding | Tony Lindgren | 2017-10-10 | 1 | -0/+93 |
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index : sinitax/cachepc-linux | |
| Fork of AMDESE/linux with modifications for CachePC side-channel attack | Louis Burda |
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