index
:
sinitax/cachepc-linux
master
Fork of AMDESE/linux with modifications for CachePC side-channel attack
Louis Burda
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
Documentation
/
devicetree
/
bindings
/
display
/
tegra
Commit message (
Expand
)
Author
Age
Files
Lines
*
dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D
Dmitry Osipenko
2021-12-17
1
-0
/
+4
*
dt-bindings: host1x: Document OPP and power domain properties
Dmitry Osipenko
2021-12-17
1
-0
/
+49
*
media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes
Sowjanya Komatineni
2021-01-04
1
-2
/
+2
*
dt-bindings: host1x: Document new interconnect properties
Dmitry Osipenko
2020-11-06
1
-0
/
+68
*
media: dt-bindings: tegra: Update VI and CSI bindings with port info
Sowjanya Komatineni
2020-08-28
1
-2
/
+90
*
dt-bindings: tegra: Add VI and CSI bindings
Sowjanya Komatineni
2020-05-12
1
-13
/
+60
*
dt-bindings: display: tegra: Support SOR crossbar configuration
Thierry Reding
2019-02-07
1
-0
/
+3
*
dt-bindings: display: tegra: Update SOR for Tegra186
Thierry Reding
2017-12-13
1
-1
/
+13
*
dt-bindings: host1x: Add Tegra186 information
Mikko Perttunen
2017-10-20
1
-0
/
+4
*
dt-bindings: Add bindings for the Tegra VIC
Mikko Perttunen
2017-04-05
1
-0
/
+13
*
dt-bindings: display: tegra: Add source clock for SOR
Thierry Reding
2016-07-14
1
-0
/
+1
*
dt-bindings: Add bindings for Tegra DPAUX pinctrl driver
Jon Hunter
2016-06-30
1
-0
/
+6
*
dt-bindings: display: Update Tegra DPAUX documentation
Jon Hunter
2016-06-30
1
-3
/
+3
*
dt-bindings: consolidate display related bindings
Rob Herring
2015-10-22
2
-0
/
+421