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| * MIPS: Store core & VP IDs in GlobalNumber-style variablePaul Burton2017-08-301-0/+22
| * MIPS: Abstract CPU core & VP(E) ID access through accessor functionsPaul Burton2017-08-309-32/+35
| * MIPS: CPS: Use GlobalNumber macros rather than magic numbersPaul Burton2017-08-301-2/+2
| * MIPS: CPS: Use change_*, set_* & clear_* where appropriatePaul Burton2017-08-302-7/+3
| * MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shiftsPaul Burton2017-08-303-5/+7
| * MIPS: CM: Use BIT/GENMASK for register fields, order & drop shiftsPaul Burton2017-08-295-39/+39
| * MIPS: CM: Specify register size when generating accessorsPaul Burton2017-08-291-6/+3
| * MIPS: CM: Rename mips_cm_base to mips_gcr_basePaul Burton2017-08-291-5/+5
| * MIPS: Declare various variables & functions staticPaul Burton2017-08-294-6/+8
| * MIPS: Remove plat_timer_setup()Paul Burton2017-08-291-14/+0
| * MIPS: Include linux/cpu.h for arch_cpu_idle()Paul Burton2017-08-291-0/+1
| * MIPS: signal: Remove unreachable code from force_fcr31_sig().Ralf Baechle2017-08-291-2/+1
| * MIPS: Remove unused ST_OFF from r2300_switch.SPaul Burton2017-08-291-6/+0
| * MIPS: Move r2300 FP code from r2300_switch.S to r2300_fpu.SPaul Burton2017-08-292-76/+79
| * MIPS: Move r4k FP code from r4k_switch.S to r4k_fpu.SPaul Burton2017-08-294-212/+211
| * MIPS: Remove unused R6000 supportPaul Burton2017-08-294-133/+0
| * MIPS: R6: Constify r2_decoder_tablesMatt Redfearn2017-08-291-4/+4
| * MIPS: SMP: Constify smp opsMatt Redfearn2017-08-296-9/+9
* | Merge branch 'work.set_fs' of git://git.kernel.org/pub/scm/linux/kernel/git/v...Linus Torvalds2017-09-141-8/+4
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| * | fs: fix kernel_read prototypeChristoph Hellwig2017-09-041-8/+4
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* | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebi...Linus Torvalds2017-09-112-11/+10
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| * | mips/signal: In force_fcr31_sig return in the impossible caseEric W. Biederman2017-08-171-1/+1
| * | signal: Remove kernel interal si_code magicEric W. Biederman2017-07-241-10/+9
| * | signal/mips: Document a conflict with SI_USER with SIGFPEEric W. Biederman2017-07-191-1/+1
* | | Merge branch 'linus' into locking/core, to fix up conflictsIngo Molnar2017-09-043-23/+4
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| * | | MIPS: Remove pt_regs adjustments in indirect syscall handlerJames Cowgill2017-08-292-17/+0
| * | | MIPS: seccomp: Fix indirect syscall argsJames Hogan2017-08-291-6/+4
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* / | smp: Avoid using two cache lines for struct call_single_dataYing Huang2017-08-291-3/+3
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* / MIPS: Fix race on setting and getting cpu_online_maskMatija Glavinic Pecotic2017-08-071-3/+3
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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2017-07-1520-409/+636
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| * MIPS: Fix MIPS I ISA /proc/cpuinfo reportingMaciej W. Rozycki2017-07-111-1/+1
| * MIPS: Traced negative syscalls should return -ENOSYSJames Hogan2017-07-111-0/+7
| * MIPS: Negate error syscall return in traceJames Hogan2017-07-111-1/+1
| * MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfoMaciej W. Rozycki2017-07-111-0/+1
| * MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructionsMaciej W. Rozycki2017-07-051-2/+37
| * MIPS: MIPS16e2: Identify ASE presenceMaciej W. Rozycki2017-07-051-0/+2
| * MIPS: Add CPU shared FTLB feature detectionPaul Burton2017-06-291-0/+11
| * MIPS: CPS: Handle spurious VP starts more gracefullyPaul Burton2017-06-291-1/+6
| * MIPS: CPS: Handle cores not powering down more gracefullyPaul Burton2017-06-291-3/+24
| * MIPS: CPS: Prevent multi-core with dcache aliasingPaul Burton2017-06-291-3/+5
| * MIPS: CM: WARN on attempt to lock invalid VP, not BUGPaul Burton2017-06-291-1/+1
| * MIPS: CM: Avoid per-core locking with CM3 & higherPaul Burton2017-06-291-6/+32
| * MIPS: Skip IPI setup if we only have 1 CPUPaul Burton2017-06-291-0/+3
| * MIPS: Use `pr_debug' for messages from `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-6/+6
| * MIPS: Fix a typo: s/preset/present/ in r2-to-r6 emulation error messageMaciej W. Rozycki2017-06-291-1/+1
| * MIPS: Send SIGILL for R6 branches in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-20/+15
| * MIPS: Send SIGILL for linked branches in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-8/+4
| * MIPS: Rename `sigill_r6' to `sigill_r2r6' in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-8/+8
| * MIPS: Send SIGILL for BPOSGE32 in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-3/+4
| * MIPS: Actually decode JALX in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-0/+1
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