| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | RISC-V: Remove the current perf implementation | Atish Patra | 2022-03-21 | 1 | -72/+0 |
| * | riscv: perf: RISCV_BASE_PMU should be independent | Kefeng Wang | 2020-05-12 | 1 | -6/+2 |
| * | riscv, perf: Add arch specific perf_arch_bpf_user_pt_regs | Björn Töpel | 2019-12-19 | 1 | -0/+4 |
| * | RISC-V: Fix !CONFIG_SMP compilation error | Atish Patra | 2018-08-13 | 1 | -0/+1 |
| * | perf: riscv: preliminary RISC-V support | Alan Kao | 2018-06-04 | 1 | -0/+84 |
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index : sinitax/cachepc-linux | |
| Fork of AMDESE/linux with modifications for CachePC side-channel attack | Louis Burda |
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