sinitax/cachepc-linux - Fork of AMDESE/linux with modifications for CachePC side-channel attack

	Commit message (Expand)	Author	Age	Files	Lines
*	xtensa: ISS: add GDBIO implementation to semihosting interface	Max Filippov	2021-04-04	1	-0/+36
*	xtensa: ISS: split simcall implementation from semihosting interface	Max Filippov	2021-04-04	1	-68/+2
*	xtensa: simcall.h: Change compitible to compatible	Bhaskar Chowdhury	2021-04-04	1	-1/+1
*	Merge tag 'xtensa-20200206' of git://github.com/jcmvbkbc/linux-xtensa	Linus Torvalds	2020-02-07	1	-5/+3
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\| *	xtensa: ISS: improve simcall assembly	Max Filippov	2020-02-04	1	-5/+3
* \|	xtensa: ISS: avoid struct timeval	Arnd Bergmann	2019-12-18	1	-2/+2
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*	xtensa: ISS: add argc/argv simcall definitions	Max Filippov	2017-03-13	1	-0/+20
*	xtensa: ISS: define simc_exit and use it instead of inline asm	Max Filippov	2016-09-20	1	-0/+5
*	xtensa: don't use a7 in simcalls	Max Filippov	2013-05-09	1	-11/+13
*	xtensa: properly fix missing compiler barrier in simcall	Max Filippov	2012-12-18	1	-6/+1
*	xtensa: ISS: fix specific simcalls	Max Filippov	2012-10-15	1	-2/+7
*	xtensa: ISS: fix __simc implementation	Max Filippov	2012-10-03	1	-0/+53
*	xtensa: move headers files to arch/xtensa/include	Chris Zankel	2008-11-06	1	-0/+62