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| | | | * | | | clk: zynqmp: Fix divider calculationRajan Vaja2020-01-231-0/+46
| | | | * | | | clk: zynqmp: Add support for get max dividerRajan Vaja2020-01-231-0/+36
| | | | * | | | clk: zynqmp: Warn user if clock user are more than allowedRajan Vaja2020-01-231-2/+4
| | | | * | | | clk: zynqmp: Extend driver for versalRajan Vaja2020-01-231-1/+2
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| | | * | | | clk: ti: clkctrl: Fix hidden dependency to node nameTony Lindgren2020-01-202-12/+88
| | | * | | | clk: ti: add clkctrl data dra7 sgxTony Lindgren2020-01-201-0/+35
| | | * | | | clk: ti: omap5: Add missing AESS clockTony Lindgren2020-01-201-0/+15
| | | * | | | clk: ti: dra7: fix parent for gmac_clkctrlGrygorii Strashko2020-01-201-1/+1
| | | * | | | clk: ti: dra7: add vpe clkctrl dataBenoit Parrot2020-01-201-0/+6
| | | * | | | clk: ti: dra7: add cam clkctrl dataBenoit Parrot2020-01-201-0/+19
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| | * | | | clk: imx: Add support for i.MX8MP clock driverAnson Huang2020-01-123-0/+771
| | * | | | clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based APIAnson Huang2020-01-121-2/+5
| | * | | | clk: imx: imx8mq: Switch to clk_hw based APIPeng Fan2019-12-231-281/+292
| | * | | | clk: imx: imx8mm: Switch to clk_hw based APIPeng Fan2019-12-231-271/+284
| | * | | | clk: imx: imx8mn: Switch to clk_hw based APIPeng Fan2019-12-231-238/+251
| | * | | | clk: imx: Remove __init for imx_obtain_fixed_clk_hw() APIPeng Fan2019-12-231-2/+2
| | * | | | clk: imx: gate3: Switch to clk_hw based APIPeng Fan2019-12-231-2/+5
| | * | | | clk: imx: add hw API imx_clk_hw_mux2_flagsPeng Fan2019-12-231-0/+10
| | * | | | clk: imx: add imx_unregister_hw_clocksPeng Fan2019-12-232-0/+9
| | * | | | clk: imx: clk-composite-8m: Switch to clk_hw based APIPeng Fan2019-12-232-9/+24
| | * | | | clk: imx: clk-pll14xx: Switch to clk_hw based APIPeng Fan2019-12-232-9/+20
| | * | | | clk: imx7up: Rename the clks to hwsAbel Vesa2019-12-111-91/+91
| | * | | | clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw basedAbel Vesa2019-12-113-6/+6
| | * | | | clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw basedAbel Vesa2019-12-113-10/+10
| | * | | | clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw basedAbel Vesa2019-12-113-4/+4
| | * | | | clk: imx: Rename sccg and frac pll register to suggest clk_hwAbel Vesa2019-12-113-7/+16
| | * | | | clk: imx: imx7ulp composite: Rename to show is clk_hw basedAbel Vesa2019-12-113-28/+28
| | * | | | clk: imx: pllv2: Switch to clk_hw based APIAbel Vesa2019-12-112-6/+13
| | * | | | clk: imx: pllv1: Switch to clk_hw based APIAbel Vesa2019-12-112-6/+13
| | * | | | clk: imx: Replace all the clk based helpers with macrosAbel Vesa2019-12-111-27/+12
| | * | | | clk: imx: Rename the SCCG to SSCGAbel Vesa2019-12-114-81/+81
| | * | | | clk: imx: Add correct failure handling for clk based helpersAbel Vesa2019-12-111-15/+22
| | * | | | clk: imx8qxp-lpcg: Warn against devm_platform_ioremap_resourceLeonard Crestez2019-12-111-0/+11
| | * | | | clk: imx8mn: correct the usb1_ctrl parent to be usb_busLi Jun2019-12-111-1/+1
| | * | | | clk: imx8m: Suppress bind attrsLeonard Crestez2019-12-093-0/+15
| | * | | | clk: imx7ulp: Fix watchdog2 clock name typoFabio Estevam2019-12-091-1/+1
| | * | | | clk: imx6q: disable non functional dividerJan Remmet2019-12-091-1/+4
| | * | | | clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHELeonard Crestez2019-12-094-2/+10
| | * | | | clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocksLeonard Crestez2019-12-093-8/+23
| | * | | | clk: imx: clk-divider-gate: drop redundant initializationPeng Fan2019-12-091-4/+4
| | * | | | clk: imx: clk-divider-gate: fix a typo in commentPeng Fan2019-12-091-1/+1
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| *-------. \ \ \ Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo...Stephen Boyd2020-01-3122-398/+468
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| | | | | | * | | | clk: sunxi: a23/a33: Export the MIPI PLLMaxime Ripard2020-01-041-1/+3
| | | | | | * | | | clk: sunxi: a31: Export the MIPI PLLMaxime Ripard2020-01-041-1/+3
| | | | | | * | | | clk: sunxi-ng: a64: export CLK_CPUX clock for DVFSVasily Khoruzhick2020-01-041-1/+0
| | | | | | * | | | clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng2020-01-041-1/+27
| | | | | | * | | | clk: sunxi-ng: r40: Export MBUS clockChen-Yu Tsai2020-01-031-4/+0
| | | | | | * | | | clk: sunxi: use of_device_get_match_dataCorentin Labbe2019-12-091-4/+2
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| | | | | * | | | clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl2020-01-071-4/+7
| | | | | * | | | Merge branch 'v5.5/fixes' into v5.6/driversJerome Brunet2019-12-162-0/+10
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