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path: root/drivers/clk
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| | * | | | | | clk: socfpga: deindent code to proper indentationStephen Boyd2019-08-161-2/+2
| | * | | | | | clk: sprd: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+3
| | * | | | | | clk: socfpga: Don't reference clk_init_data after registrationStephen Boyd2019-08-162-13/+16
| | * | | | | | clk: sirf: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-4/+8
| | * | | | | | clk: qcom: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+2
| | * | | | | | clk: meson: axg-audio: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+5
| | * | | | | | clk: lochnagar: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-1/+1
| | * | | | | | clk: actions: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+3
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| *-------. \ \ \ \ \ Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-me...Stephen Boyd2019-09-1967-1420/+9861
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| | | | | | * | | | | | clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocksNeil Armstrong2019-08-262-1/+61
| | | | | | * | | | | | clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clockNeil Armstrong2019-08-262-1/+198
| | | | | | * | | | | | clk: meson: g12a: add support for SM1 GP1 PLLNeil Armstrong2019-08-262-1/+310
| | | | | | * | | | | | clk: meson: axg-audio: add g12a reset supportJerome Brunet2019-08-202-2/+106
| | | | | * | | | | | | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil2019-08-124-4/+4
| | | | | * | | | | | | clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil2019-08-071-1/+8
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| | | | * | | | | | | clk: mvebu: ap80x: add AP807 clock supportBen Peled2019-09-171-0/+28
| | | | * | | | | | | clk: mvebu: ap806: Prepare the introduction of AP807 clock supportBen Peled2019-09-171-63/+77
| | | | * | | | | | | clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driverOmri Itach2019-09-171-2/+46
| | | | * | | | | | | clk: mvebu: ap806: be more explicit on what SaR isMiquel Raynal2019-09-171-1/+1
| | | | * | | | | | | clk: mvebu: ap80x-cpu: add AP807 CPU clock supportBen Peled2019-09-171-2/+57
| | | | * | | | | | | clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clockChristine Gharzuzi2019-09-171-20/+62
| | | | * | | | | | | clk: mvebu: ap806: Fix clock name for the clusterGregory CLEMENT2019-08-081-2/+2
| | | | * | | | | | | clk: mvebu: add CPU clock driver for Armada 7K/8KGregory CLEMENT2019-08-083-0/+263
| | | | * | | | | | | clk: mvebu: add helper file for Armada AP and CP clocksGregory CLEMENT2019-08-086-42/+61
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| | | * | | | | | | clk: mediatek: Runtime PM support for MT8183 mcucfg clock providerWeiyi Lu2019-09-171-2/+5
| | | * | | | | | | clk: mediatek: Register clock gate with deviceWeiyi Lu2019-09-174-6/+23
| | | * | | | | | | clk: mediatek: add pericfg clocks for MT8183Chunfeng Yun2019-09-171-0/+30
| | | * | | | | | | clk: mediatek: Add MT6779 clock supportmtk017612019-09-0911-0/+1974
| | | * | | | | | | clk: reset: Modify reset-controller driveryong.liang2019-08-083-4/+71
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| | * | | | | | | clk: qcom: rcg: Return failure for RCG updateTaniya Das2019-09-171-1/+1
| | * | | | | | | clk: qcom: fix QCS404 TuringCC regmapJorge Ramirez-Ortiz2019-09-091-1/+1
| | * | | | | | | clk: qcom: clk-rpmh: Add support for SM8150Vinod Koul2019-09-091-0/+28
| | * | | | | | | clk: qcom: clk-rpmh: Convert to parent data schemeVinod Koul2019-09-091-2/+8
| | * | | | | | | clk: qcom: gcc: Use floor ops for SDCC clocksTaniya Das2019-09-094-6/+6
| | * | | | | | | clk: qcom: gcc-qcs404: Use floor ops for sdcc clksVinod Koul2019-09-091-2/+2
| | * | | | | | | clk: qcom: gcc-sdm845: Use floor ops for sdcc clksStephen Boyd2019-09-091-2/+2
| | * | | | | | | clk: qcom: define probe by index API as common APIGovind Singh2019-08-083-21/+24
| | * | | | | | | clk: qcom: Add WCSS gcc clock control for QCS404Govind Singh2019-08-081-0/+30
| | * | | | | | | clk: qcom: msm8916: Don't build by defaultMarc Gonzalez2019-08-071-2/+0
| | * | | | | | | clk: qcom: gcc: Add global clock controller driver for SM8150Deepak Katragadda2019-08-073-0/+3596
| | * | | | | | | clk: qcom: clk-alpha-pll: Add support for Trion PLLsDeepak Katragadda2019-08-072-0/+224
| | * | | | | | | clk: qcom: clk-alpha-pll: Remove post_div_table checksVinod Koul2019-08-071-15/+0
| | * | | | | | | clk: qcom: clk-alpha-pll: Remove unnecessary castVinod Koul2019-08-071-2/+2
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| *-----. \ \ \ \ \ \ Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put', 'clk-const-bulk...Stephen Boyd2019-09-1910-34/+50
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| | | | | * | | | | clk: Drop !clk checks in debugfs dumpingStephen Boyd2019-09-191-12/+0
| | | | | * | | | | clk: Use seq_puts() in possible_parent_show()Markus Elfring2019-08-081-5/+5
| | | | | * | | | | clk: Assert prepare_lock in clk_core_get_boundariesLeonard Crestez2019-08-081-0/+2
| | | | | * | | | | clk: Add clk_min/max_rate entries in debugfsLeonard Crestez2019-08-081-0/+36
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| | | * | | | | | clk: ti: dm814x: Add of_node_put() to prevent memory leakNishka Dasgupta2019-08-071-0/+1
| | | * | | | | | clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup()Nishka Dasgupta2019-08-071-0/+1
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