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| | | | * | | clk: imx: off by one in imx_lpcg_parse_clks_from_dt()Dan Carpenter2022-03-041-1/+1
| | | | * | | clk: imx7d: Remove audio_mclk_root_clkAbel Vesa2022-03-041-1/+0
| | | | * | | clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clockLaurent Pinchart2022-02-211-0/+1
| | | | * | | clk: imx: Add imx8dxl clk driverJacky Bai2022-01-294-1/+70
| | | | * | | clk: imx: Add initial support for i.MXRT1050 clock driverJesse Taube2022-01-293-0/+176
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| | | * | | clk: Mark clk_core_evict_parent_cache_subtree() 'target' constStephen Boyd2022-02-251-1/+1
| | | * | | clk: Mark 'all_lists' as constStephen Boyd2022-02-251-2/+2
| | | * | | clk: pistachio: Declare mux table as const u32[]Jonathan Neuschäfer2022-02-251-1/+1
| | | * | | clk: qcom: Declare mux table as const u32[]Jonathan Neuschäfer2022-02-251-1/+1
| | | * | | clk: mmp: Declare mux tables as const u32[]Jonathan Neuschäfer2022-02-251-2/+2
| | | * | | clk: hisilicon: Remove unnecessary cast of mux table to u32 *Jonathan Neuschäfer2022-02-251-1/+1
| | | * | | clk: mux: Declare u32 *table parameter as constJonathan Neuschäfer2022-02-251-5/+5
| | | * | | clk: nxp: Declare mux table parameter as const u32 *Jonathan Neuschäfer2022-02-251-1/+1
| | | * | | clk: nxp: Remove unused variableJonathan Neuschäfer2022-02-251-2/+1
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| | * / / clk: mvebu: use time_is_before_eq_jiffies() instead of open coding itWang Qing2022-02-171-1/+2
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| *-----. \ \ Merge branches 'clk-xilinx', 'clk-kunit', 'clk-cs2000' and 'clk-renesas' into...Stephen Boyd2022-03-2920-309/+1290
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| | | | | * | clk: rs9: Add Renesas 9-series PCIe clock generator driverMarek Vasut2022-03-183-0/+332
| | | | | * | clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()Marek Vasut2022-03-181-0/+22
| | | | | * | clk: renesas: r8a779f0: Add PFC clockGeert Uytterhoeven2022-02-221-0/+1
| | | | | * | clk: renesas: r8a779f0: Add I2C clocksGeert Uytterhoeven2022-02-221-0/+6
| | | | | * | clk: renesas: r8a779f0: Add WDT clockGeert Uytterhoeven2022-02-221-0/+9
| | | | | * | clk: renesas: r8a779f0: Fix RSW2 clock dividerGeert Uytterhoeven2022-02-221-1/+1
| | | | | * | clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-105-191/+250
| | | | | * | clk: renesas: r8a779a0: Add CANFD module clockUlrich Hecht2022-01-241-0/+1
| | | | | * | clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3Lad Prabhakar2022-01-241-2/+2
| | | | | * | clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko2022-01-242-0/+2
| | | | | * | clk: renesas: r8a779f0: Add SYS-DMAC clocksYoshihiro Shimoda2022-01-241-0/+2
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| | | | * | clk: cs2000-cp: convert driver to regmapDaniel Mack2022-01-252-56/+69
| | | | * | clk: cs2000-cp: freeze config during register fiddlingDaniel Mack2022-01-251-0/+9
| | | | * | clk: cs2000-cp: make clock skip setting configurableDaniel Mack2022-01-251-1/+4
| | | | * | clk: cs2000-cp: add support for dynamic modeDaniel Mack2022-01-251-37/+74
| | | | * | clk: cs2000-cp: Make aux output function controllableDaniel Mack2022-01-251-0/+9
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| | | * / clk: gate: Add some kunit test suitesStephen Boyd2022-01-244-0/+476
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| | * / clk: zynqmp: replace warn_once with pr_debug for failed clock opsMichael Tretter2022-01-244-32/+32
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| *-------. \ Merge branches 'clk-microchip', 'clk-si', 'clk-mtk', 'clk-at91' and 'clk-st' ...Stephen Boyd2022-03-2966-460/+1411
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| | | | | | * clk: stm32mp1: Add parent_data to ETHRX clockMarek Vasut2022-01-241-4/+32
| | | | | | * clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clockMarek Vasut2022-01-241-3/+7
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| | | | | * clk: at91: clk-master: remove dead codeClaudiu Beznea2022-03-0813-134/+18
| | | | | * clk: at91: sama7g5: fix parents of PDMCs' GCLKCodrin Ciubotariu2022-03-081-4/+4
| | | | | * clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DTTudor Ambarus2022-01-241-1/+7
| | | | | * clk: at91: allow setting PMC_AUDIOPINCK clock parents via DTZixun LI2022-01-241-1/+3
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| | | | * clk: mediatek: Warn if clk IDs are duplicatedChen-Yu Tsai2022-02-175-6/+34
| | | | * clk: mediatek: mt8195: Implement remove functionsChen-Yu Tsai2022-02-175-0/+83
| | | | * clk: mediatek: mt8195: Implement error handling in probe functionsChen-Yu Tsai2022-02-175-18/+61
| | | | * clk: mediatek: mt8195: Hook up mtk_clk_simple_remove()Chen-Yu Tsai2022-02-1714-0/+14
| | | | * clk: mediatek: Unregister clks in mtk_clk_simple_probe() error pathChen-Yu Tsai2022-02-171-1/+3
| | | | * clk: mediatek: mtk: Implement error handling in register APIsChen-Yu Tsai2022-02-172-35/+103
| | | | * clk: mediatek: pll: Implement error handling in register APIChen-Yu Tsai2022-02-172-7/+22
| | | | * clk: mediatek: mux: Implement error handling in register APIChen-Yu Tsai2022-02-171-1/+14
| | | | * clk: mediatek: mux: Reverse check for existing clk to reduce nesting levelChen-Yu Tsai2022-02-171-7/+8
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-01-12 06:23:18 +0000