summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
| | * | | clk: imx: Rework all clk_hw_register_mux wrappersAbel Vesa2021-09-301-46/+22
| | * | | clk: imx: Rework all clk_hw_register_gate2 wrappersAbel Vesa2021-09-301-51/+26
| | * | | clk: imx: Rework all clk_hw_register_gate wrappersAbel Vesa2021-09-171-41/+23
| | * | | clk: imx: Make mux/mux2 clk based helpers use clk_hw based onesAbel Vesa2021-09-171-20/+6
| | * | | clk: imx: Remove unused helpersAbel Vesa2021-09-171-103/+0
| | |/ /
| | | |
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| *-----. \ \ Merge branches 'clk-leak', 'clk-rockchip', 'clk-renesas' and 'clk-at91' into ...Stephen Boyd2021-11-0237-412/+1543
| |\ \ \ \ \ \
| | | | | * | | clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea2021-10-261-1/+1
| | | | | * | | clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea2021-10-261-10/+1
| | | | | * | | clk: at91: clk-master: add notifier for dividerClaudiu Beznea2021-10-2613-82/+186
| | | | | * | | clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea2021-10-264-29/+95
| | | | | * | | clk: at91: clk-master: fix prescaler logicClaudiu Beznea2021-10-261-1/+1
| | | | | * | | clk: at91: clk-master: mask mckr against layout->maskClaudiu Beznea2021-10-261-2/+5
| | | | | * | | clk: at91: clk-master: check if div or pres is zeroClaudiu Beznea2021-10-261-2/+2
| | | | | * | | clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULLClaudiu Beznea2021-10-261-2/+2
| | | | | * | | clk: at91: pmc: add sama7g5 to the list of available pmcsClaudiu Beznea2021-10-261-2/+3
| | | | | * | | clk: at91: clk-master: improve readability by using local variablesClaudiu Beznea2021-10-261-3/+3
| | | | | * | | clk: at91: clk-master: add register definition for sama7g5's master clockClaudiu Beznea2021-10-261-27/+23
| | | | | * | | clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea2021-10-261-0/+1
| | | | | * | | clk: at91: pmc: execute suspend/resume only for backup modeClaudiu Beznea2021-10-261-0/+39
| | | | | * | | clk: at91: re-factor clocks suspend/resumeClaudiu Beznea2021-10-2612-181/+558
| | | | | * | | clk: at91: check pmc node status before registering syscore opsClément Léger2021-10-071-0/+5
| | | | | |/ /
| | | | * | | clk: renesas: r8a779[56]x: Add MLP clocksAndrey Gusakov2021-10-153-0/+3
| | | | * | | clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das2021-10-082-0/+40
| | | | * | | clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das2021-10-082-0/+130
| | | | * | | clk: renesas: r8a779a0: Add RPC supportWolfram Sang2021-10-081-0/+32
| | | | * | | clk: renesas: cpg-lib: Move RPC clock registration to the libraryWolfram Sang2021-10-083-87/+92
| | | | * | | clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar2021-10-082-0/+21
| | | | * | | clk: renesas: r8a779a0: Add Z0 and Z1 clock supportGeert Uytterhoeven2021-09-281-0/+158
| | | | * | | clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das2021-09-241-0/+10
| | | | * | | clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das2021-09-242-1/+81
| | | | * | | clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das2021-09-242-1/+21
| | | | * | | clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das2021-09-242-0/+35
| | | | * | | clk: renesas: r8a779a0: Add TPU clockWolfram Sang2021-09-241-0/+1
| | | * | | | clk: rockchip: use module_platform_driver_probeMiles Chen2021-09-212-2/+2
| | | * | | | clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}Brian Norris2021-09-201-2/+2
| | | * | | | clk: rockchip: rk3399: make CPU clocks criticalBrian Norris2021-09-201-4/+7
| | | | |/ / | | | |/| |
| | * / | | clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling pathsChristophe JAILLET2021-09-141-3/+11
| | |/ / /
| | | | |
| | \ \ \
| | \ \ \
| | \ \ \
| *---. | | | Merge branches 'clk-qcom', 'clk-mtk', 'clk-versatile' and 'clk-doc' into clk-...Stephen Boyd2021-11-0242-24/+3189
| |\ \ \| | |
| | | * | | | clk: versatile: hide clock drivers from non-ARM usersJean Delvare2021-10-141-0/+1
| | | * | | | clk: versatile: Rename ICST to CLK_ICSTJean Delvare2021-10-142-2/+2
| | | * | | | clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for regis...Rob Herring2021-09-141-1/+2
| | | |/ / /
| | * | | | clk: mediatek: Export clk_ops structures to modulesStephen Boyd2021-09-141-0/+2
| | * | | | clk: mediatek: support COMMON_CLK_MT6779 module buildMiles Chen2021-09-1410-17/+35
| | * | | | clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen2021-09-148-1/+33
| | * | | | clk: composite: export clk_register_compositeMiles Chen2021-09-141-0/+1
| | * | | | clk: mediatek: Add MT8195 apusys clock supportChun-Jie Chen2021-09-142-1/+94
| | * | | | clk: mediatek: Add MT8195 imp i2c wrapper clock supportChun-Jie Chen2021-09-142-1/+69
| | * | | | clk: mediatek: Add MT8195 wpesys clock supportChun-Jie Chen2021-09-142-1/+145
| | * | | | clk: mediatek: Add MT8195 vppsys1 clock supportChun-Jie Chen2021-09-142-1/+109
| | * | | | clk: mediatek: Add MT8195 vppsys0 clock supportChun-Jie Chen2021-09-142-1/+111
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-01-14 09:29:19 +0000