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| | | | * | clk: bcm2835: Switch to clk_divider.determine_rateMartin Blumenstingl2021-08-051-5/+4
| | | | * | clk: divider: Implement and wire up .determine_rate by defaultMartin Blumenstingl2021-08-051-0/+23
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| | | * / clk: palmas: Add a missing SPDX license headerJason Wang2021-08-051-9/+1
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| | * | clk: renesas: Make CLK_R9A06G032 invisibleGeert Uytterhoeven2021-08-131-3/+1
| | * | clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar2021-07-261-1/+2
| | * | clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar2021-07-191-0/+6
| | * | clk: renesas: r9a07g044: Add clock and reset entries for CANFDLad Prabhakar2021-07-191-0/+4
| | * | clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven2021-07-194-3/+3
| | * | clk: renesas: r9a07g044: Add GPIO clock and reset entriesLad Prabhakar2021-07-191-0/+5
| | * | clk: renesas: r9a07g044: Add SSIF-2 clock and reset entriesBiju Das2021-07-191-0/+20
| | * | clk: renesas: r9a07g044: Add USB clocks/resetsBiju Das2021-07-191-0/+12
| | * | clk: renesas: r9a07g044: Add DMAC clocks/resetsBiju Das2021-07-191-0/+8
| | * | clk: renesas: r9a07g044: Add I2C clocks/resetsBiju Das2021-07-191-0/+12
| | * | clk: renesas: r8a779a0: Add the DSI clocksKieran Bingham2021-07-191-1/+3
| | * | clk: renesas: r8a779a0: Add the DU clockKieran Bingham2021-07-191-0/+1
| | * | clk: renesas: rzg2: Rename i2c-dvfs to iic-pmicGeert Uytterhoeven2021-07-194-4/+4
| | * | clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()Lad Prabhakar2021-07-191-1/+1
| | * | clk: renesas: rzg2l: Avoid mixing error pointers and NULLDan Carpenter2021-07-191-1/+1
| | * | clk: renesas: rzg2l: Fix a double free on errorDan Carpenter2021-07-191-7/+1
| | * | clk: renesas: rzg2l: Fix return value and unused assignmentYang Li2021-07-191-4/+2
| | * | clk: renesas: rzg2l: Remove unneeded semicolonYang Li2021-07-191-1/+1
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| *-------. \ \ Merge branches 'clk-qcom', 'clk-socfpga', 'clk-mediatek', 'clk-lmk' and 'clk-...Stephen Boyd2021-09-0148-439/+17910
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| | | | | | * | clk: x86: Rename clk-lpt to more specific clk-lpss-atomAndy Shevchenko2021-07-272-7/+7
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| | | | | * / clk: lmk04832: drop redundant fallthrough statementsLiam Beguin2021-07-271-18/+0
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| | | | * | clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167Miles Chen2021-07-271-15/+10
| | | | * | clk: mediatek: Add MT8192 vencsys clock supportChun-Jie Chen2021-07-273-0/+60
| | | | * | clk: mediatek: Add MT8192 vdecsys clock supportChun-Jie Chen2021-07-273-0/+101
| | | | * | clk: mediatek: Add MT8192 scp adsp clock supportChun-Jie Chen2021-07-273-0/+57
| | | | * | clk: mediatek: Add MT8192 msdc clock supportChun-Jie Chen2021-07-273-0/+92
| | | | * | clk: mediatek: Add MT8192 mmsys clock supportChun-Jie Chen2021-07-273-0/+115
| | | | * | clk: mediatek: Add MT8192 mfgcfg clock supportChun-Jie Chen2021-07-273-0/+57
| | | | * | clk: mediatek: Add MT8192 mdpsys clock supportChun-Jie Chen2021-07-273-0/+89
| | | | * | clk: mediatek: Add MT8192 ipesys clock supportChun-Jie Chen2021-07-273-0/+64
| | | | * | clk: mediatek: Add MT8192 imp i2c wrapper clock supportChun-Jie Chen2021-07-273-0/+126
| | | | * | clk: mediatek: Add MT8192 imgsys clock supportChun-Jie Chen2021-07-273-0/+77
| | | | * | clk: mediatek: Add MT8192 camsys clock supportChun-Jie Chen2021-07-273-0/+114
| | | | * | clk: mediatek: Add MT8192 audio clock supportChun-Jie Chen2021-07-273-0/+125
| | | | * | clk: mediatek: Add MT8192 basic clocks supportChun-Jie Chen2021-07-275-4/+1358
| | | | * | clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providersChun-Jie Chen2021-07-272-0/+31
| | | | * | clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen2021-07-272-14/+21
| | | | * | clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen2021-07-271-4/+16
| | | | * | clk: mediatek: Get regmap without syscon compatible checkChun-Jie Chen2021-07-274-4/+4
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| | | * | clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen2021-07-261-1/+1
| | | * | clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen2021-07-261-0/+9
| | | * | clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen2021-07-261-4/+4
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| | * | clk: qcom: Add SM6350 GCC driverKonrad Dybcio2021-08-293-0/+2596
| | * | clk: qcom: rpmh: Add support for RPMH clocks on SM6350Konrad Dybcio2021-08-281-0/+21
| | * | clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250Lukas Bulwahn2021-08-281-2/+2
| | * | clk: qcom: Add Global Clock controller (GCC) driver for SM6115Iskren Chernev2021-08-283-0/+3552
| | * | clk: qcom: mmcc-msm8994: Add MSM8992 supportKonrad Dybcio2021-08-261-0/+126
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-01-14 23:17:36 +0000