| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSC | Guo, Bing | 2021-11-24 | 1 | -28/+0 |
| * | drm/amd/display: move FPU associated DSC code to DML folder | Qingqing Zhuo | 2021-10-28 | 1 | -259/+0 |
| * | drm/amd/display: take max dsc stream bandwidth overhead into account | Wenjing Liu | 2021-04-28 | 1 | -43/+0 |
| * | drm/amd/display: Fix compilation error | Tao.Huang | 2020-11-02 | 1 | -3/+3 |
| * | drm/amd/display: Use u16 for drm_bpp in DSC calculations | Nicholas Kazlauskas | 2020-07-01 | 1 | -4/+4 |
| * | drm/amd/display: Rework dsc to isolate FPU operations | Rodrigo Siqueira | 2020-07-01 | 1 | -6/+145 |
| * | drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED | Bhawanpreet Lakha | 2019-11-13 | 1 | -2/+0 |
| * | drm/amd/display: Remove set but not used variable 'source_bpp' | zhengbin | 2019-10-07 | 1 | -3/+0 |
| * | drm/amd/display: Add DSC support for Navi (v2) | Harry Wentland | 2019-06-22 | 1 | -0/+258 |
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index : sinitax/cachepc-linux | |
| Fork of AMDESE/linux with modifications for CachePC side-channel attack | Louis Burda |
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