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path: root/drivers/gpu/drm/amd/include/asic_reg/dcn
Commit message (Expand)AuthorAgeFilesLines
* drm/amd/display: Add HDMI_ACP_SEND registerAlan Liu2022-05-264-2/+8
* drm/amd/include: add DCN 3.1.5 registersQingqing Zhuo2022-02-182-0/+77252
* drm/amd/include: Add register headers for DCN 3.1.6Leo Li2022-02-172-0/+78399
* drm/amdgpu: move dpcs_3_0_3 headers from dcn to dpcsAlex Deucher2022-02-072-1396/+0
* drm/amdgpu: move dpcs_3_0_0 headers from dcn to dpcsAlex Deucher2022-02-072-4152/+0
* drm/amdgpu: add missing license to dpcs_3_0_0 headersAlex Deucher2022-02-072-0/+14
* drm/amd/display: Disable hdmistream and hdmichar clocksJake Wang2021-10-192-0/+10
* drm/amdgpu: add cyan_skillfish asic header filesZhan Liu2021-09-292-0/+28284
* drm/amd/display: DMUB Outbound Interrupt Process-X86Chun-Liang Chang2021-07-081-0/+4
* drm/amd/display: Add interface to get Calibrated Avg Level from FIFOWesley Chalmers2021-06-152-0/+4
* drm/amdgpu: add yellow carp asic header files (v3)Aaron Liu2021-06-042-0/+75830
* drm/amd/display: Edit license info for beige goby DC filesAurabindo Pillai2021-05-194-37/+18
* drm/amd/display: Add register definitions for Beige GobyAurabindo Pillai2021-05-194-0/+45172
* drm/amd/amdgpu: Add missing BASE_IDX to dcn registerTom St Denis2021-03-051-1/+1
* drm/amdgpu: Add and use seperate reg headers for dcn302Bhawanpreet Lakha2020-11-102-0/+78535
* drm/amdgpu: add vangogh asic header files (v2)Huang Rui2020-10-052-0/+66628
* drm/amd/display: remove unintended executable modeLukas Bulwahn2020-08-244-0/+0
* drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3Bhawanpreet Lakha2020-08-171-0/+22
* drm/amd/display: Add dcn30 Headers (v2)Jerry (Fangzhi) Zuo2020-06-034-0/+92947
* drm/amd/include: Add OCSC registersRodrigo Siqueira2020-01-164-2/+24
* drm/amdgpu: move dpcs headers to dpcs includesRoman Li2019-12-182-3995/+0
* drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha2019-10-171-0/+10
* drm/amd/display: Add Renoir registers (v3)Bhawanpreet Lakha2019-08-294-0/+74495
* drm/amd/display: Create DWB resource for DCN2Charlene Liu2019-06-222-0/+20
* drm/amdgpu: add DCN 2.0 register headersHawking Zhang2019-06-202-0/+85539
* drm/amd/include: Add HUBPREQ_DEBUG register offsetsLeo Li2019-04-231-0/+8
* drm/amdgpu: Add CM_TEST_DEBUG regs for DCNHarry Wentland2018-04-112-3/+24
* drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROLHarry Wentland2018-02-191-0/+14
* drm/amd/include:cleanup raven1 dcn header files.Feifei Xu2017-12-062-0/+68414
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