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path: root/drivers/gpu/drm/amd/include/asic_reg/gc
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* drm/amdgpu: add gc v11_0_0 ip headers v11Hawking Zhang2022-04-283-0/+59419
* drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debuggingTom St Denis2021-08-052-0/+58
* drm/amdgpu: only harvest gcea/mmea error status in arcturusHawking Zhang2021-04-201-0/+16
* drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headersTom St Denis2021-04-092-0/+15
* drm/amdgpu: add gc v9_4_2 ip headers (v3)Hawking Zhang2021-03-102-0/+40632
* drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher2020-10-233-0/+36
* drm/amdgpu: add missing newline at eofTom Rix2020-10-151-1/+1
* drm/amdgpu: update athub interrupt harvesting handleStanley.Yang2020-09-221-1/+3
* drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher2020-09-173-0/+56
* drm/amd/amdgpu: Add RLC_CGTT_MGCG_OVERRIDE to gfx 10.3 headersTom St Denis2020-07-272-0/+27
* drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)Tom St Denis2020-07-012-4/+4
* drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registersTom St Denis2020-07-015-13/+26
* drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bitsTom St Denis2020-07-0110-5/+109
* drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)Tom St Denis2020-07-0110-0/+59
* drm/amdgpu: add GC 10.3 header files (v2)Likun Gao2020-06-033-0/+68433
* drm/amd/amdgpu: Add missing GRBM bits for GFX 10.1Tom St Denis2020-05-111-0/+4
* drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own headerTom St Denis2020-04-012-7/+0
* drm/amd/amdgpu: Add GFX9.1 PWR_MISC_CNTL_STATUS register to headersTom St Denis2020-04-012-0/+7
* drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for ArcturusJoseph Greathouse2020-01-301-2/+4
* drm/amdgpu: add EDC counter registers of gc for ArcturusDennis Li2020-01-222-0/+1012
* drm/amdgpu: add defines for DF and TCP HashingJoseph Greathouse2020-01-141-0/+6
* drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support ArcturusJames Zhu2019-12-231-0/+8
* drm/amd/include: add register define for VML2 and ATCL2Dennis Li2019-10-152-4/+32
* drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2019-08-022-0/+41
* drm/amd/include: add define of TCP_EDC_CNT_NEWDennis Li2019-07-311-0/+2
* drm/amd/include: add bitfield define for EDC registersDennis Li2019-07-311-0/+157
* drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang2019-06-203-0/+61330
* drm/amdgpu: add EDC counter registerJames Zhu2019-05-241-0/+31
* drm/amdgpu: add CP_DEBUG register definition for GC9.0Tao Zhou2018-10-101-0/+2
* drm/amd/include: update the bitfield define for PF_MAX_REGIONShaoyun Liu2018-09-101-2/+2
* drm/amd/include: Add ip header files for vega12.Feifei Xu2018-03-212-0/+38657
* drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header filesTom St Denis2018-03-071-0/+31150
* drm/amdgpu: remove some old gc 9.x registersAlex Deucher2017-12-134-80/+0
* drm/amd/include:cleanup raven1 gc header files.Feifei Xu2017-12-061-0/+7491
* drm/amd/include:cleanup vega10 gc header files.Feifei Xu2017-12-063-0/+40971
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