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path: root/drivers/gpu/drm/msm/dsi/phy
Commit message (Expand)AuthorAgeFilesLines
* drm/msm/dsi: pll_7nm: remove unsupported dividers for DSI pixel clockDmitry Baryshkov2022-05-071-6/+4
* drm/msm/dsi: fix address for second DSI PHY on SDM660Dmitry Baryshkov2022-05-071-1/+1
*-. Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-d...Dmitry Baryshkov2022-02-197-19/+151
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| | * drm/msm/dsi/phy: fix 7nm v4.0 settings for C-PHY modeDmitry Baryshkov2022-02-181-8/+14
| | * drm/msm/dsi: Add 10nm dsi phy tuning configuration supportRajeev Nandan2022-02-181-6/+112
| | * drm/msm/dsi: Add dsi phy tuning configuration supportRajeev Nandan2022-02-182-0/+10
| | * drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parentMarijn Suijten2022-02-185-5/+15
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* / drm/msm: drop dbgname argument from msm_ioremap*()Dmitry Baryshkov2022-02-181-4/+4
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* drm/msm/dsi: invalid parameter check in msm_dsi_phy_enableJosé Expósito2022-01-251-1/+3
* drm/msm: Don't use autosuspend for displayRob Clark2021-12-161-1/+1
* drm/msm/dsi: stop setting clock parents manuallyDmitry Baryshkov2021-11-281-11/+0
* drm/msm/dsi: Add phy configuration for MSM8953Vladimir Lypak2021-10-153-0/+24
* drm/msm/dsi: Use division result from div_u64_rem in 7nm and 14nm PLLMarijn Suijten2021-10-152-6/+2
* drm/msm/dsi: dsi_phy_14nm: Take ready-bit into account in poll_for_readyMarijn Suijten2021-10-111-15/+15
* drm/msm/dsi/phy: fix clock names in 28nm_8960 phyDmitry Baryshkov2021-10-111-2/+2
* drm/msm/dsi: add continuous clock support for 7nm PHYDmitry Baryshkov2021-08-103-0/+27
* drm/msm/dsi: Fix DSI and DSI PHY regulator config from SDM660Konrad Dybcio2021-08-071-1/+1
* drm/msm/dsi: rename dual DSI to bonded DSIDmitry Baryshkov2021-08-073-5/+5
* drm/msm/dsi: Add PHY configuration for SC7280Rajeev Nandan2021-08-073-0/+29
* drm/msm/dsi: drop msm_dsi_phy_get_shared_timingsDmitry Baryshkov2021-08-071-8/+5
* drm/msm/dsi: phy: use of_device_get_match_dataDmitry Baryshkov2021-08-071-6/+4
* drm/msm/dsi: support CPHY mode for 7nm pll/phyJonathan Marek2021-08-073-43/+154
* drm/msm: Generated register updateRob Clark2021-06-236-0/+6
* drm/msm/dsi: fix 32-bit clang warningArnd Bergmann2021-06-231-1/+5
* Merge branch 'msm-fixes-v5.13-rc6' into msm-next-redoRob Clark2021-06-232-0/+2
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| * drm/msm/dsi: Stash away calculated vco frequency on recalcStephen Boyd2021-06-102-0/+2
* | drm/msm/dsi: add DSI PHY registers to snapshot dataDmitry Baryshkov2021-06-232-4/+31
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* drm/msm/dsi: fix msm_dsi_phy_get_clk_provider return codeDmitry Baryshkov2021-04-271-1/+1
* drm/msm/dsi: dsi_phy_28nm_8960: fix uninitialized variable accessDmitry Baryshkov2021-04-271-0/+4
* drm/msm/dsi: stop passing src_pll_id to the phy_enable callDmitry Baryshkov2021-04-078-12/+12
* drm/msm/dsi: inline msm_dsi_phy_set_src_pllDmitry Baryshkov2021-04-078-46/+21
* drm/msm/dsi: remove temp data from global pll structureDmitry Baryshkov2021-04-073-447/+220
* drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instancesDmitry Baryshkov2021-04-075-149/+119
* drm/msm/dsi: move ioremaps to dsi_phy_driver_probeDmitry Baryshkov2021-04-077-163/+108
* drm/msm/dsi: drop PLL accessor functionsDmitry Baryshkov2021-04-076-303/+283
* drm/msm/dsi: drop msm_dsi_pll abstractionDmitry Baryshkov2021-04-078-248/+221
* drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phyDmitry Baryshkov2021-04-077-83/+64
* drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepareDmitry Baryshkov2021-04-076-161/+171
* drm/msm/dsi: simplify vco_delay handling in dsi_phy_28nm driverDmitry Baryshkov2021-04-071-8/+4
* drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm driversDmitry Baryshkov2021-04-073-10/+0
* drm/msm/dsi: make save/restore_state phy-level functionsDmitry Baryshkov2021-04-076-49/+38
* drm/msm/dsi: use devm_of_clk_add_hw_providerDmitry Baryshkov2021-04-071-21/+1
* drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocksDmitry Baryshkov2021-04-079-245/+71
* drm/msm/dsi: push provided clocks handling into a generic codeDmitry Baryshkov2021-04-079-275/+70
* drm/msm/dsi: remove msm_dsi_pll_set_usecaseDmitry Baryshkov2021-04-075-20/+3
* drm/msm/dsi: move min/max PLL rate to phy configDmitry Baryshkov2021-04-078-23/+27
* drm/msm/dsi: drop global msm_dsi_phy_type enumarationDmitry Baryshkov2021-04-077-33/+25
* drm/msm/dsi: move all PLL callbacks into PHY config structDmitry Baryshkov2021-04-079-204/+191
* drm/msm/dsi: drop multiple pll enable_seq supportDmitry Baryshkov2021-04-075-56/+42
* drm/msm/dsi: fuse dsi_pll_* code into dsi_phy_* codeDmitry Baryshkov2021-04-077-0/+4339
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