sinitax/cachepc-linux - Fork of AMDESE/linux with modifications for CachePC side-channel attack

	Commit message (Collapse)	Author	Age	Files	Lines
*	interconnect: qcom: Add OSM L3 support on SM8150	Sibi Sankar	2020-09-08	1	-0/+2
\| \| \| \| \| \| \| \| \|	Add Operation State Manager (OSM) L3 interconnect provider support on SM8150 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200801123049.32398-3-sibis@codeaurora.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
*	interconnect: qcom: Add SM8150 interconnect provider driver	Jonathan Marek	2020-09-08	1	-0/+152
	Add driver for the Qualcomm interconnect buses found in SM8150 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Based on SC7180 driver and generated from downstream dts. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200728023811.5607-5-jonathan@marek.ca Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>