| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | PCI: Check for platform_get_irq() failure consistently | Aman Sharma | 2020-05-12 | 1 | -2/+2 |
| * | PCI: mobiveil: Fix unmet dependency warning for PCIE_MOBIVEIL_PLAT | Hou Zhiqiang | 2020-03-18 | 1 | -0/+1 |
| * | PCI: mobiveil: Fix sparse different address space warnings | Hou Zhiqiang | 2020-03-17 | 1 | -3/+4 |
| * | PCI: mobiveil: Add PCIe Gen4 RC driver for Layerscape SoCs | Hou Zhiqiang | 2020-02-21 | 4 | -2/+291 |
| * | PCI: mobiveil: Add Header Type field check | Hou Zhiqiang | 2020-02-21 | 1 | -0/+13 |
| * | PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors | Hou Zhiqiang | 2020-02-21 | 1 | -0/+23 |
| * | PCI: mobiveil: Allow mobiveil_host_init() to be used to re-init host | Hou Zhiqiang | 2020-02-21 | 2 | -7/+13 |
| * | PCI: mobiveil: Add callback function for link up check | Hou Zhiqiang | 2020-02-21 | 2 | -0/+8 |
| * | PCI: mobiveil: Add callback function for interrupt initialization | Hou Zhiqiang | 2020-02-21 | 2 | -1/+18 |
| * | PCI: mobiveil: Modularize the Mobiveil PCIe Host Bridge IP driver | Hou Zhiqiang | 2020-02-21 | 6 | -0/+1102 |
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index : sinitax/cachepc-linux | |
| Fork of AMDESE/linux with modifications for CachePC side-channel attack | Louis Burda |
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