| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | bus: ti-sysc: Add parsing of module capabilities | Tony Lindgren | 2017-12-21 | 1 | -0/+10 |
| * | bus: ti-sysc: Handle module quirks based dts configuration | Tony Lindgren | 2017-12-21 | 1 | -0/+6 |
| * | bus: ti-sysc: Detect i2c interconnect target module based on register layout | Tony Lindgren | 2017-12-21 | 1 | -0/+1 |
| * | bus: ti-sysc: Add register bits for interconnect target modules | Tony Lindgren | 2017-12-21 | 1 | -0/+40 |
| * | bus: ti-sysc: Make omap_hwmod_sysc_fields into sysc_regbits platform data | Tony Lindgren | 2017-12-21 | 1 | -0/+29 |
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index : sinitax/cachepc-linux | |
| Fork of AMDESE/linux with modifications for CachePC side-channel attack | Louis Burda |
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