sinitax/cachepc-linux - Fork of AMDESE/linux with modifications for CachePC side-channel attack

	Commit message (Expand)	Author	Age	Files	Lines
*	net: phy: Add 10BASE-T1L support in phy-c45	Alexandru Tachici	2022-05-01	1	-0/+10
*	net: phy: Add BaseT1 auto-negotiation registers	Alexandru Tachici	2022-05-01	1	-0/+40
*	net: phy: Add 10-BaseT1L registers	Alexandru Tachici	2022-05-01	1	-0/+25
*	net: phy: add constants for fast retrain related register	Luo Jie	2021-10-25	1	-0/+9
*	net: phy: add constants for 2.5G and 5G speed in PCS speed register	Marek Behún	2021-04-08	1	-0/+2
*	net: phy: add USXGMII link partner ability constants	Michael Walle	2020-07-19	1	-0/+26
*	net: phy: add EEE-related constants	Heiner Kallweit	2019-08-19	1	-0/+10
*	net: phy: Add generic support for 2.5GBaseT and 5GBaseT	Maxime Chevallier	2019-02-13	1	-0/+16
*	net: phy: disregard "Clause 22 registers present" bit in get_phy_c45_devs_in_pkg	Heiner Kallweit	2019-02-08	1	-0/+1
*	net: phy: let genphy_c45_read_link manage the devices to check	Heiner Kallweit	2019-02-07	1	-0/+2
*	License cleanup: add SPDX license identifier to uapi header files with a license	Greg Kroah-Hartman	2017-11-02	1	-0/+1
*	UAPI: (Scripted) Disintegrate include/linux	David Howells	2012-10-13	1	-0/+297