| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | perf arm-spe: Add SPE total latency as PERF_SAMPLE_WEIGHT | Namhyung Kim | 2021-12-16 | 1 | -0/+1 |
| * | perf arm-spe: Save context ID in record | German Gomez | 2021-11-13 | 1 | -0/+1 |
| * | perf arm-spe: Store operation type in packet | Leo Yan | 2021-02-12 | 1 | -0/+6 |
| * | perf arm-spe: Store memory address in packet | Leo Yan | 2021-02-12 | 1 | -0/+2 |
| * | perf arm-spe: Refactor event type handling | Leo Yan | 2020-11-26 | 1 | -17/+0 |
| * | perf arm-spe: Support synthetic events | Tan Xiaojun | 2020-06-01 | 1 | -0/+82 |
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index : sinitax/cachepc-linux | |
| Fork of AMDESE/linux with modifications for CachePC side-channel attack | Louis Burda |
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