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* cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams2022-05-191-2/+3
* cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams2022-05-191-6/+3
* cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams2022-05-191-4/+4
* cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams2022-05-192-10/+16
* cxl/pci: Move cxl_await_media_ready() to the coreDan Williams2022-05-192-7/+15
* tools/testing/cxl: Add a physical_node linkDan Williams2022-02-081-2/+19
* tools/testing/cxl: Enumerate mock decodersDan Williams2022-02-081-20/+98
* tools/testing/cxl: Mock one level of switchesDan Williams2022-02-081-41/+97
* tools/testing/cxl: Fix root port to host bridge assignmentDan Williams2022-02-081-1/+1
* tools/testing/cxl: Mock dvsec_ranges()Dan Williams2022-02-081-0/+10
* cxl/memdev: Add numa_node attributeDan Williams2022-02-081-0/+1
* cxl/pci: Emit device serial numberDan Williams2022-02-081-0/+1
* cxl/pci: Implement wait for media activeBen Widawsky2022-02-081-0/+8
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-083-30/+21
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-081-2/+0
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-083-0/+82
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-083-49/+69
* cxl/test: Mock acpi_table_parse_cedt()Dan Williams2021-11-153-46/+58
* tools/testing/cxl: add mock output for the GET_HEALTH_INFO commandVishal Verma2021-11-151-0/+49
* cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny2021-11-151-25/+25
* tools/testing/cxl: Introduce a mock memory device + driverDan Williams2021-09-213-1/+328
* tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams2021-09-214-0/+713
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