cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

target_arch_reg.h (2934B)

      1/*
      2 *  FreeBSD amd64 register structures
      3 *
      4 *  Copyright (c) 2015 Stacey Son
      5 *  All rights reserved.
      6 *
      7 *  This program is free software; you can redistribute it and/or modify
      8 *  it under the terms of the GNU General Public License as published by
      9 *  the Free Software Foundation; either version 2 of the License, or
     10 *  (at your option) any later version.
     11 *
     12 *  This program is distributed in the hope that it will be useful,
     13 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15 *  GNU General Public License for more details.
     16 *
     17 *  You should have received a copy of the GNU General Public License
     18 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#ifndef _TARGET_ARCH_REG_H_
     22#define _TARGET_ARCH_REG_H_
     23
     24/* See sys/amd64/include/reg.h */
     25typedef struct target_reg {
     26    uint64_t        r_r15;
     27    uint64_t        r_r14;
     28    uint64_t        r_r13;
     29    uint64_t        r_r12;
     30    uint64_t        r_r11;
     31    uint64_t        r_r10;
     32    uint64_t        r_r9;
     33    uint64_t        r_r8;
     34    uint64_t        r_rdi;
     35    uint64_t        r_rsi;
     36    uint64_t        r_rbp;
     37    uint64_t        r_rbx;
     38    uint64_t        r_rdx;
     39    uint64_t        r_rcx;
     40    uint64_t        r_rax;
     41    uint32_t        r_trapno;
     42    uint16_t        r_fs;
     43    uint16_t        r_gs;
     44    uint32_t        r_err;
     45    uint16_t        r_es;
     46    uint16_t        r_ds;
     47    uint64_t        r_rip;
     48    uint64_t        r_cs;
     49    uint64_t        r_rflags;
     50    uint64_t        r_rsp;
     51    uint64_t        r_ss;
     52} target_reg_t;
     53
     54typedef struct target_fpreg {
     55    uint64_t        fpr_env[4];
     56    uint8_t         fpr_acc[8][16];
     57    uint8_t         fpr_xacc[16][16];
     58    uint64_t        fpr_spare[12];
     59} target_fpreg_t;
     60
     61static inline void target_copy_regs(target_reg_t *regs, const CPUX86State *env)
     62{
     63
     64    regs->r_r15 = env->regs[15];
     65    regs->r_r14 = env->regs[14];
     66    regs->r_r13 = env->regs[13];
     67    regs->r_r12 = env->regs[12];
     68    regs->r_r11 = env->regs[11];
     69    regs->r_r10 = env->regs[10];
     70    regs->r_r9 = env->regs[9];
     71    regs->r_r8 = env->regs[8];
     72    regs->r_rdi = env->regs[R_EDI];
     73    regs->r_rsi = env->regs[R_ESI];
     74    regs->r_rbp = env->regs[R_EBP];
     75    regs->r_rbx = env->regs[R_EBX];
     76    regs->r_rdx = env->regs[R_EDX];
     77    regs->r_rcx = env->regs[R_ECX];
     78    regs->r_rax = env->regs[R_EAX];
     79    /* regs->r_trapno = env->regs[R_TRAPNO]; XXX */
     80    regs->r_fs = env->segs[R_FS].selector & 0xffff;
     81    regs->r_gs = env->segs[R_GS].selector & 0xffff;
     82    regs->r_err = env->error_code;  /* XXX ? */
     83    regs->r_es = env->segs[R_ES].selector & 0xffff;
     84    regs->r_ds = env->segs[R_DS].selector & 0xffff;
     85    regs->r_rip = env->eip;
     86    regs->r_cs = env->segs[R_CS].selector & 0xffff;
     87    regs->r_rflags = env->eflags;
     88    regs->r_rsp = env->regs[R_ESP];
     89    regs->r_ss = env->segs[R_SS].selector & 0xffff;
     90}
     91
     92#endif /* !_TARGET_ARCH_REG_H_ */