cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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nuvoton.rst (3139B)


      1Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
      2================================================================
      3
      4The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
      5designed to be used as Baseboard Management Controllers (BMCs) in various
      6servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an
      7assortment of peripherals targeted for either Enterprise or Data Center /
      8Hyperscale applications. The former is a superset of the latter, so NPCM750 has
      9all the peripherals of NPCM730 and more.
     10
     11.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
     12
     13The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
     14segment. The following machines are based on this chip :
     15
     16- ``npcm750-evb``       Nuvoton NPCM750 Evaluation board
     17
     18The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
     19Hyperscale applications. The following machines are based on this chip :
     20
     21- ``quanta-gbs-bmc``    Quanta GBS server BMC
     22- ``quanta-gsj``        Quanta GSJ server BMC
     23- ``kudo-bmc``          Fii USA Kudo server BMC
     24
     25There are also two more SoCs, NPCM710 and NPCM705, which are single-core
     26variants of NPCM750 and NPCM730, respectively. These are currently not
     27supported by QEMU.
     28
     29Supported devices
     30-----------------
     31
     32 * SMP (Dual Core Cortex-A9)
     33 * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer
     34   and Watchdog.
     35 * SRAM, ROM and DRAM mappings
     36 * System Global Control Registers (GCR)
     37 * Clock and reset controller (CLK)
     38 * Timer controller (TIM)
     39 * Serial ports (16550-based)
     40 * DDR4 memory controller (dummy interface indicating memory training is done)
     41 * OTP controllers (no protection features)
     42 * Flash Interface Unit (FIU; no protection features)
     43 * Random Number Generator (RNG)
     44 * USB host (USBH)
     45 * GPIO controller
     46 * Analog to Digital Converter (ADC)
     47 * Pulse Width Modulation (PWM)
     48 * SMBus controller (SMBF)
     49 * Ethernet controller (EMC)
     50 * Tachometer
     51
     52Missing devices
     53---------------
     54
     55 * LPC/eSPI host-to-BMC interface, including
     56
     57   * Keyboard and mouse controller interface (KBCI)
     58   * Keyboard Controller Style (KCS) channels
     59   * BIOS POST code FIFO
     60   * System Wake-up Control (SWC)
     61   * Shared memory (SHM)
     62   * eSPI slave interface
     63
     64 * Ethernet controller (GMAC)
     65 * USB device (USBD)
     66 * Peripheral SPI controller (PSPI)
     67 * SD/MMC host
     68 * PECI interface
     69 * PCI and PCIe root complex and bridges
     70 * VDM and MCTP support
     71 * Serial I/O expansion
     72 * LPC/eSPI host
     73 * Coprocessor
     74 * Graphics
     75 * Video capture
     76 * Encoding compression engine
     77 * Security features
     78
     79Boot options
     80------------
     81
     82The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
     83a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` and
     84possibly others can be downloaded from the OpenPOWER jenkins :
     85
     86   https://openpower.xyz/
     87
     88The firmware image should be attached as an MTD drive. Example :
     89
     90.. code-block:: bash
     91
     92  $ qemu-system-arm -machine quanta-gsj -nographic \
     93      -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw
     94
     95The default root password for test images is usually ``0penBmc``.