cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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arm-vfp3.xml (1886B)


      1<?xml version="1.0"?>
      2<!-- Copyright (C) 2008 Free Software Foundation, Inc.
      3
      4     Copying and distribution of this file, with or without modification,
      5     are permitted in any medium without royalty provided the copyright
      6     notice and this notice are preserved.  -->
      7<!DOCTYPE feature SYSTEM "gdb-target.dtd">
      8<feature name="org.gnu.gdb.arm.vfp">
      9  <reg name="d0" bitsize="64" type="float"/>
     10  <reg name="d1" bitsize="64" type="float"/>
     11  <reg name="d2" bitsize="64" type="float"/>
     12  <reg name="d3" bitsize="64" type="float"/>
     13  <reg name="d4" bitsize="64" type="float"/>
     14  <reg name="d5" bitsize="64" type="float"/>
     15  <reg name="d6" bitsize="64" type="float"/>
     16  <reg name="d7" bitsize="64" type="float"/>
     17  <reg name="d8" bitsize="64" type="float"/>
     18  <reg name="d9" bitsize="64" type="float"/>
     19  <reg name="d10" bitsize="64" type="float"/>
     20  <reg name="d11" bitsize="64" type="float"/>
     21  <reg name="d12" bitsize="64" type="float"/>
     22  <reg name="d13" bitsize="64" type="float"/>
     23  <reg name="d14" bitsize="64" type="float"/>
     24  <reg name="d15" bitsize="64" type="float"/>
     25  <reg name="d16" bitsize="64" type="float"/>
     26  <reg name="d17" bitsize="64" type="float"/>
     27  <reg name="d18" bitsize="64" type="float"/>
     28  <reg name="d19" bitsize="64" type="float"/>
     29  <reg name="d20" bitsize="64" type="float"/>
     30  <reg name="d21" bitsize="64" type="float"/>
     31  <reg name="d22" bitsize="64" type="float"/>
     32  <reg name="d23" bitsize="64" type="float"/>
     33  <reg name="d24" bitsize="64" type="float"/>
     34  <reg name="d25" bitsize="64" type="float"/>
     35  <reg name="d26" bitsize="64" type="float"/>
     36  <reg name="d27" bitsize="64" type="float"/>
     37  <reg name="d28" bitsize="64" type="float"/>
     38  <reg name="d29" bitsize="64" type="float"/>
     39  <reg name="d30" bitsize="64" type="float"/>
     40  <reg name="d31" bitsize="64" type="float"/>
     41
     42  <reg name="fpscr" bitsize="32" type="int" group="float"/>
     43</feature>