cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

power-fpu.xml (2088B)

      1<?xml version="1.0"?>
      2<!-- Copyright (C) 2007, 2008 Free Software Foundation, Inc.
      3
      4     Copying and distribution of this file, with or without modification,
      5     are permitted in any medium without royalty provided the copyright
      6     notice and this notice are preserved.  -->
      7
      8<!DOCTYPE feature SYSTEM "gdb-target.dtd">
      9<feature name="org.gnu.gdb.power.fpu">
     10  <reg name="f0" bitsize="64" type="ieee_double" regnum="71"/>
     11  <reg name="f1" bitsize="64" type="ieee_double"/>
     12  <reg name="f2" bitsize="64" type="ieee_double"/>
     13  <reg name="f3" bitsize="64" type="ieee_double"/>
     14  <reg name="f4" bitsize="64" type="ieee_double"/>
     15  <reg name="f5" bitsize="64" type="ieee_double"/>
     16  <reg name="f6" bitsize="64" type="ieee_double"/>
     17  <reg name="f7" bitsize="64" type="ieee_double"/>
     18  <reg name="f8" bitsize="64" type="ieee_double"/>
     19  <reg name="f9" bitsize="64" type="ieee_double"/>
     20  <reg name="f10" bitsize="64" type="ieee_double"/>
     21  <reg name="f11" bitsize="64" type="ieee_double"/>
     22  <reg name="f12" bitsize="64" type="ieee_double"/>
     23  <reg name="f13" bitsize="64" type="ieee_double"/>
     24  <reg name="f14" bitsize="64" type="ieee_double"/>
     25  <reg name="f15" bitsize="64" type="ieee_double"/>
     26  <reg name="f16" bitsize="64" type="ieee_double"/>
     27  <reg name="f17" bitsize="64" type="ieee_double"/>
     28  <reg name="f18" bitsize="64" type="ieee_double"/>
     29  <reg name="f19" bitsize="64" type="ieee_double"/>
     30  <reg name="f20" bitsize="64" type="ieee_double"/>
     31  <reg name="f21" bitsize="64" type="ieee_double"/>
     32  <reg name="f22" bitsize="64" type="ieee_double"/>
     33  <reg name="f23" bitsize="64" type="ieee_double"/>
     34  <reg name="f24" bitsize="64" type="ieee_double"/>
     35  <reg name="f25" bitsize="64" type="ieee_double"/>
     36  <reg name="f26" bitsize="64" type="ieee_double"/>
     37  <reg name="f27" bitsize="64" type="ieee_double"/>
     38  <reg name="f28" bitsize="64" type="ieee_double"/>
     39  <reg name="f29" bitsize="64" type="ieee_double"/>
     40  <reg name="f30" bitsize="64" type="ieee_double"/>
     41  <reg name="f31" bitsize="64" type="ieee_double"/>
     42
     43  <reg name="fpscr" bitsize="32" group="float"/>
     44</feature>