cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

rx-core.xml (2830B)


      1<?xml version="1.0"?>
      2<!-- Copyright (C) 2019 Free Software Foundation, Inc.
      3
      4     Copying and distribution of this file, with or without modification,
      5     are permitted in any medium without royalty provided the copyright
      6     notice and this notice are preserved.  -->
      7
      8<!DOCTYPE feature SYSTEM "gdb-target.dtd">
      9<feature name="org.gnu.gdb.rx.core">
     10  <reg name="r0" bitsize="32" type="data_ptr"/>
     11  <reg name="r1" bitsize="32" type="uint32"/>
     12  <reg name="r2" bitsize="32" type="uint32"/>
     13  <reg name="r3" bitsize="32" type="uint32"/>
     14  <reg name="r4" bitsize="32" type="uint32"/>
     15  <reg name="r5" bitsize="32" type="uint32"/>
     16  <reg name="r6" bitsize="32" type="uint32"/>
     17  <reg name="r7" bitsize="32" type="uint32"/>
     18  <reg name="r8" bitsize="32" type="uint32"/>
     19  <reg name="r9" bitsize="32" type="uint32"/>
     20  <reg name="r10" bitsize="32" type="uint32"/>
     21  <reg name="r11" bitsize="32" type="uint32"/>
     22  <reg name="r12" bitsize="32" type="uint32"/>
     23  <reg name="r13" bitsize="32" type="uint32"/>
     24  <reg name="r14" bitsize="32" type="uint32"/>
     25  <reg name="r15" bitsize="32" type="uint32"/>
     26
     27  <flags id="psw_flags" size="4">
     28    <field name="C" start="0" end="0"/>
     29    <field name="Z" start="1" end="1"/>
     30    <field name="S" start="2" end="2"/>
     31    <field name="O" start="3" end="3"/>
     32    <field name="I" start="16" end="16"/>
     33    <field name="U" start="17" end="17"/>
     34    <field name="PM" start="20" end="20"/>
     35    <field name="IPL" start="24" end="27"/>
     36  </flags>
     37
     38  <flags id="fpsw_flags" size="4">
     39    <field name="RM" start="0" end="1"/>
     40    <field name="CV" start="2" end="2"/>
     41    <field name="CO" start="3" end="3"/>
     42    <field name="CZ" start="4" end="4"/>
     43    <field name="CU" start="5" end="5"/>
     44    <field name="CX" start="6" end="6"/>
     45    <field name="CE" start="7" end="7"/>
     46    <field name="DN" start="8" end="8"/>
     47    <field name="EV" start="10" end="10"/>
     48    <field name="EO" start="11" end="11"/>
     49    <field name="EZ" start="12" end="12"/>
     50    <field name="EU" start="13" end="13"/>
     51    <field name="EX" start="14" end="14"/>
     52    <field name="FV" start="26" end="26"/>
     53    <field name="FO" start="27" end="27"/>
     54    <field name="FZ" start="28" end="28"/>
     55    <field name="FU" start="29" end="29"/>
     56    <field name="FX" start="30" end="30"/>
     57    <field name="FS" start="31" end="31"/>
     58  </flags>
     59
     60  <reg name="usp" bitsize="32" type="data_ptr"/>
     61  <reg name="isp" bitsize="32" type="data_ptr"/>
     62  <reg name="psw" bitsize="32" type="psw_flags"/>
     63  <reg name="pc" bitsize="32" type="code_ptr"/>
     64  <reg name="intb" bitsize="32" type="data_ptr"/>
     65  <reg name="bpsw" bitsize="32" type="psw_flags"/>
     66  <reg name="bpc" bitsize="32" type="code_ptr"/>
     67  <reg name="fintv" bitsize="32" type="code_ptr"/>
     68  <reg name="fpsw" bitsize="32" type="fpsw_flags"/>
     69  <reg name="acc" bitsize="64" type="uint64"/>
     70</feature>