exynos4_boards.c (6321B)
1/* 2 * Samsung exynos4 SoC based boards emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 24#include "qemu/osdep.h" 25#include "qemu/units.h" 26#include "qapi/error.h" 27#include "qemu/error-report.h" 28#include "hw/sysbus.h" 29#include "net/net.h" 30#include "hw/arm/boot.h" 31#include "exec/address-spaces.h" 32#include "hw/arm/exynos4210.h" 33#include "hw/net/lan9118.h" 34#include "hw/qdev-properties.h" 35#include "hw/boards.h" 36#include "hw/irq.h" 37 38#define SMDK_LAN9118_BASE_ADDR 0x05000000 39 40typedef enum Exynos4BoardType { 41 EXYNOS4_BOARD_NURI, 42 EXYNOS4_BOARD_SMDKC210, 43 EXYNOS4_NUM_OF_BOARDS 44} Exynos4BoardType; 45 46typedef struct Exynos4BoardState { 47 Exynos4210State soc; 48 MemoryRegion dram0_mem; 49 MemoryRegion dram1_mem; 50} Exynos4BoardState; 51 52static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = { 53 [EXYNOS4_BOARD_NURI] = 0xD33, 54 [EXYNOS4_BOARD_SMDKC210] = 0xB16, 55}; 56 57static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = { 58 [EXYNOS4_BOARD_NURI] = EXYNOS4210_SECOND_CPU_BOOTREG, 59 [EXYNOS4_BOARD_SMDKC210] = EXYNOS4210_SECOND_CPU_BOOTREG, 60}; 61 62static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = { 63 [EXYNOS4_BOARD_NURI] = 1 * GiB, 64 [EXYNOS4_BOARD_SMDKC210] = 1 * GiB, 65}; 66 67static struct arm_boot_info exynos4_board_binfo = { 68 .loader_start = EXYNOS4210_BASE_BOOT_ADDR, 69 .smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR, 70 .nb_cpus = EXYNOS4210_NCPUS, 71 .write_secondary_boot = exynos4210_write_secondary, 72}; 73 74static void lan9215_init(uint32_t base, qemu_irq irq) 75{ 76 DeviceState *dev; 77 SysBusDevice *s; 78 79 /* This should be a 9215 but the 9118 is close enough */ 80 if (nd_table[0].used) { 81 qemu_check_nic_model(&nd_table[0], "lan9118"); 82 dev = qdev_new(TYPE_LAN9118); 83 qdev_set_nic_properties(dev, &nd_table[0]); 84 qdev_prop_set_uint32(dev, "mode_16bit", 1); 85 s = SYS_BUS_DEVICE(dev); 86 sysbus_realize_and_unref(s, &error_fatal); 87 sysbus_mmio_map(s, 0, base); 88 sysbus_connect_irq(s, 0, irq); 89 } 90} 91 92static void exynos4_boards_init_ram(Exynos4BoardState *s, 93 MemoryRegion *system_mem, 94 unsigned long ram_size) 95{ 96 unsigned long mem_size = ram_size; 97 98 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { 99 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", 100 mem_size - EXYNOS4210_DRAM_MAX_SIZE, 101 &error_fatal); 102 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, 103 &s->dram1_mem); 104 mem_size = EXYNOS4210_DRAM_MAX_SIZE; 105 } 106 107 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, 108 &error_fatal); 109 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, 110 &s->dram0_mem); 111} 112 113static Exynos4BoardState * 114exynos4_boards_init_common(MachineState *machine, 115 Exynos4BoardType board_type) 116{ 117 Exynos4BoardState *s = g_new(Exynos4BoardState, 1); 118 119 exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type]; 120 exynos4_board_binfo.board_id = exynos4_board_id[board_type]; 121 exynos4_board_binfo.smp_bootreg_addr = 122 exynos4_board_smp_bootreg_addr[board_type]; 123 exynos4_board_binfo.gic_cpu_if_addr = 124 EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100; 125 126 exynos4_boards_init_ram(s, get_system_memory(), 127 exynos4_board_ram_size[board_type]); 128 129 object_initialize_child(OBJECT(machine), "soc", &s->soc, 130 TYPE_EXYNOS4210_SOC); 131 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 132 133 return s; 134} 135 136static void nuri_init(MachineState *machine) 137{ 138 exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI); 139 140 arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo); 141} 142 143static void smdkc210_init(MachineState *machine) 144{ 145 Exynos4BoardState *s = exynos4_boards_init_common(machine, 146 EXYNOS4_BOARD_SMDKC210); 147 148 lan9215_init(SMDK_LAN9118_BASE_ADDR, 149 qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)])); 150 arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo); 151} 152 153static void nuri_class_init(ObjectClass *oc, void *data) 154{ 155 MachineClass *mc = MACHINE_CLASS(oc); 156 157 mc->desc = "Samsung NURI board (Exynos4210)"; 158 mc->init = nuri_init; 159 mc->max_cpus = EXYNOS4210_NCPUS; 160 mc->min_cpus = EXYNOS4210_NCPUS; 161 mc->default_cpus = EXYNOS4210_NCPUS; 162 mc->ignore_memory_transaction_failures = true; 163} 164 165static const TypeInfo nuri_type = { 166 .name = MACHINE_TYPE_NAME("nuri"), 167 .parent = TYPE_MACHINE, 168 .class_init = nuri_class_init, 169}; 170 171static void smdkc210_class_init(ObjectClass *oc, void *data) 172{ 173 MachineClass *mc = MACHINE_CLASS(oc); 174 175 mc->desc = "Samsung SMDKC210 board (Exynos4210)"; 176 mc->init = smdkc210_init; 177 mc->max_cpus = EXYNOS4210_NCPUS; 178 mc->min_cpus = EXYNOS4210_NCPUS; 179 mc->default_cpus = EXYNOS4210_NCPUS; 180 mc->ignore_memory_transaction_failures = true; 181} 182 183static const TypeInfo smdkc210_type = { 184 .name = MACHINE_TYPE_NAME("smdkc210"), 185 .parent = TYPE_MACHINE, 186 .class_init = smdkc210_class_init, 187}; 188 189static void exynos4_machines_init(void) 190{ 191 type_register_static(&nuri_type); 192 type_register_static(&smdkc210_type); 193} 194 195type_init(exynos4_machines_init)