cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

kzm.c (4686B)

      1/*
      2 * KZM Board System emulation.
      3 *
      4 * Copyright (c) 2008 OKL and 2011 NICTA
      5 * Written by Hans at OK-Labs
      6 * Updated by Peter Chubb.
      7 *
      8 * This code is licensed under the GPL, version 2 or later.
      9 * See the file `COPYING' in the top level directory.
     10 *
     11 * It (partially) emulates a Kyoto Microcomputer
     12 * KZM-ARM11-01 evaluation board, with a Freescale
     13 * i.MX31 SoC
     14 */
     15
     16#include "qemu/osdep.h"
     17#include "qapi/error.h"
     18#include "hw/arm/fsl-imx31.h"
     19#include "hw/boards.h"
     20#include "qemu/error-report.h"
     21#include "exec/address-spaces.h"
     22#include "net/net.h"
     23#include "hw/net/lan9118.h"
     24#include "hw/char/serial.h"
     25#include "sysemu/qtest.h"
     26#include "sysemu/sysemu.h"
     27#include "qemu/cutils.h"
     28
     29/* Memory map for Kzm Emulation Baseboard:
     30 * 0x00000000-0x7fffffff See i.MX31 SOC for support
     31 * 0x80000000-0x8fffffff RAM                  EMULATED
     32 * 0x90000000-0x9fffffff RAM                  EMULATED
     33 * 0xa0000000-0xafffffff Flash                IGNORED
     34 * 0xb0000000-0xb3ffffff Unavailable          IGNORED
     35 * 0xb4000000-0xb4000fff 8-bit free space     IGNORED
     36 * 0xb4001000-0xb400100f Board control        IGNORED
     37 *  0xb4001003           DIP switch
     38 * 0xb4001010-0xb400101f 7-segment LED        IGNORED
     39 * 0xb4001020-0xb400102f LED                  IGNORED
     40 * 0xb4001030-0xb400103f LED                  IGNORED
     41 * 0xb4001040-0xb400104f FPGA, UART           EMULATED
     42 * 0xb4001050-0xb400105f FPGA, UART           EMULATED
     43 * 0xb4001060-0xb40fffff FPGA                 IGNORED
     44 * 0xb6000000-0xb61fffff LAN controller       EMULATED
     45 * 0xb6200000-0xb62fffff FPGA NAND Controller IGNORED
     46 * 0xb6300000-0xb7ffffff Free                 IGNORED
     47 * 0xb8000000-0xb8004fff Memory control registers IGNORED
     48 * 0xc0000000-0xc3ffffff PCMCIA/CF            IGNORED
     49 * 0xc4000000-0xffffffff Reserved             IGNORED
     50 */
     51
     52typedef struct IMX31KZM {
     53    FslIMX31State soc;
     54    MemoryRegion ram_alias;
     55} IMX31KZM;
     56
     57#define KZM_RAM_ADDR            (FSL_IMX31_SDRAM0_ADDR)
     58#define KZM_FPGA_ADDR           (FSL_IMX31_CS4_ADDR + 0x1040)
     59#define KZM_LAN9118_ADDR        (FSL_IMX31_CS5_ADDR)
     60
     61static struct arm_boot_info kzm_binfo = {
     62    .loader_start = KZM_RAM_ADDR,
     63    .board_id = 1722,
     64};
     65
     66static void kzm_init(MachineState *machine)
     67{
     68    IMX31KZM *s = g_new0(IMX31KZM, 1);
     69    unsigned int ram_size;
     70    unsigned int alias_offset;
     71    unsigned int i;
     72
     73    object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX31);
     74
     75    qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
     76
     77    /* Check the amount of memory is compatible with the SOC */
     78    if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) {
     79        char *sz = size_to_str(FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE);
     80        error_report("RAM size more than %s is not supported", sz);
     81        g_free(sz);
     82        exit(EXIT_FAILURE);
     83    }
     84
     85    memory_region_add_subregion(get_system_memory(), FSL_IMX31_SDRAM0_ADDR,
     86                                machine->ram);
     87
     88    /* initialize the alias memory if any */
     89    for (i = 0, ram_size = machine->ram_size, alias_offset = 0;
     90         (i < 2) && ram_size; i++) {
     91        unsigned int size;
     92        static const struct {
     93            hwaddr addr;
     94            unsigned int size;
     95        } ram[2] = {
     96            { FSL_IMX31_SDRAM0_ADDR, FSL_IMX31_SDRAM0_SIZE },
     97            { FSL_IMX31_SDRAM1_ADDR, FSL_IMX31_SDRAM1_SIZE },
     98        };
     99
    100        size = MIN(ram_size, ram[i].size);
    101
    102        ram_size -= size;
    103
    104        if (size < ram[i].size) {
    105            memory_region_init_alias(&s->ram_alias, NULL, "ram.alias",
    106                                     machine->ram,
    107                                     alias_offset, ram[i].size - size);
    108            memory_region_add_subregion(get_system_memory(),
    109                                        ram[i].addr + size, &s->ram_alias);
    110        }
    111
    112        alias_offset += ram[i].size;
    113    }
    114
    115    if (nd_table[0].used) {
    116        lan9118_init(&nd_table[0], KZM_LAN9118_ADDR,
    117                     qdev_get_gpio_in(DEVICE(&s->soc.avic), 52));
    118    }
    119
    120    if (serial_hd(2)) { /* touchscreen */
    121        serial_mm_init(get_system_memory(), KZM_FPGA_ADDR+0x10, 0,
    122                       qdev_get_gpio_in(DEVICE(&s->soc.avic), 52),
    123                       14745600, serial_hd(2), DEVICE_NATIVE_ENDIAN);
    124    }
    125
    126    kzm_binfo.ram_size = machine->ram_size;
    127    kzm_binfo.nb_cpus = 1;
    128
    129    if (!qtest_enabled()) {
    130        arm_load_kernel(&s->soc.cpu, machine, &kzm_binfo);
    131    }
    132}
    133
    134static void kzm_machine_init(MachineClass *mc)
    135{
    136    mc->desc = "ARM KZM Emulation Baseboard (ARM1136)";
    137    mc->init = kzm_init;
    138    mc->ignore_memory_transaction_failures = true;
    139    mc->default_ram_id = "kzm.ram";
    140}
    141
    142DEFINE_MACHINE("kzm", kzm_machine_init)