cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

microbit.c (2531B)

      1/*
      2 * BBC micro:bit machine
      3 * http://tech.microbit.org/hardware/
      4 *
      5 * Copyright 2018 Joel Stanley <joel@jms.id.au>
      6 *
      7 * This code is licensed under the GPL version 2 or later.  See
      8 * the COPYING file in the top-level directory.
      9 */
     10
     11#include "qemu/osdep.h"
     12#include "qapi/error.h"
     13#include "hw/boards.h"
     14#include "hw/arm/boot.h"
     15#include "sysemu/sysemu.h"
     16#include "exec/address-spaces.h"
     17
     18#include "hw/arm/nrf51_soc.h"
     19#include "hw/i2c/microbit_i2c.h"
     20#include "hw/qdev-properties.h"
     21#include "qom/object.h"
     22
     23struct MicrobitMachineState {
     24    MachineState parent;
     25
     26    NRF51State nrf51;
     27    MicrobitI2CState i2c;
     28};
     29
     30#define TYPE_MICROBIT_MACHINE MACHINE_TYPE_NAME("microbit")
     31
     32OBJECT_DECLARE_SIMPLE_TYPE(MicrobitMachineState, MICROBIT_MACHINE)
     33
     34static void microbit_init(MachineState *machine)
     35{
     36    MicrobitMachineState *s = MICROBIT_MACHINE(machine);
     37    MemoryRegion *system_memory = get_system_memory();
     38    MemoryRegion *mr;
     39
     40    object_initialize_child(OBJECT(machine), "nrf51", &s->nrf51,
     41                            TYPE_NRF51_SOC);
     42    qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
     43    object_property_set_link(OBJECT(&s->nrf51), "memory",
     44                             OBJECT(system_memory), &error_fatal);
     45    sysbus_realize(SYS_BUS_DEVICE(&s->nrf51), &error_fatal);
     46
     47    /*
     48     * Overlap the TWI stub device into the SoC.  This is a microbit-specific
     49     * hack until we implement the nRF51 TWI controller properly and the
     50     * magnetometer/accelerometer devices.
     51     */
     52    object_initialize_child(OBJECT(machine), "microbit.twi", &s->i2c,
     53                            TYPE_MICROBIT_I2C);
     54    sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &error_fatal);
     55    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0);
     56    memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
     57                                        mr, -1);
     58
     59    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
     60                       s->nrf51.flash_size);
     61}
     62
     63static void microbit_machine_class_init(ObjectClass *oc, void *data)
     64{
     65    MachineClass *mc = MACHINE_CLASS(oc);
     66
     67    mc->desc = "BBC micro:bit (Cortex-M0)";
     68    mc->init = microbit_init;
     69    mc->max_cpus = 1;
     70}
     71
     72static const TypeInfo microbit_info = {
     73    .name = TYPE_MICROBIT_MACHINE,
     74    .parent = TYPE_MACHINE,
     75    .instance_size = sizeof(MicrobitMachineState),
     76    .class_init = microbit_machine_class_init,
     77};
     78
     79static void microbit_machine_init(void)
     80{
     81    type_register_static(&microbit_info);
     82}
     83
     84type_init(microbit_machine_init);