cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

msf2-som.c (4224B)

      1/*
      2 * SmartFusion2 SOM starter kit(from Emcraft) emulation.
      3 *
      4 * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#include "qemu/osdep.h"
     26#include "qemu/units.h"
     27#include "qapi/error.h"
     28#include "qemu/error-report.h"
     29#include "hw/boards.h"
     30#include "hw/qdev-properties.h"
     31#include "hw/arm/boot.h"
     32#include "hw/qdev-clock.h"
     33#include "exec/address-spaces.h"
     34#include "hw/arm/msf2-soc.h"
     35
     36#define DDR_BASE_ADDRESS      0xA0000000
     37#define DDR_SIZE              (64 * MiB)
     38
     39#define M2S010_ENVM_SIZE      (256 * KiB)
     40#define M2S010_ESRAM_SIZE     (64 * KiB)
     41
     42static void emcraft_sf2_s2s010_init(MachineState *machine)
     43{
     44    DeviceState *dev;
     45    DeviceState *spi_flash;
     46    MSF2State *soc;
     47    MachineClass *mc = MACHINE_GET_CLASS(machine);
     48    DriveInfo *dinfo = drive_get_next(IF_MTD);
     49    qemu_irq cs_line;
     50    BusState *spi_bus;
     51    MemoryRegion *sysmem = get_system_memory();
     52    MemoryRegion *ddr = g_new(MemoryRegion, 1);
     53    Clock *m3clk;
     54
     55    if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
     56        error_report("This board can only be used with CPU %s",
     57                     mc->default_cpu_type);
     58        exit(1);
     59    }
     60
     61    memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
     62                           &error_fatal);
     63    memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
     64
     65    dev = qdev_new(TYPE_MSF2_SOC);
     66    qdev_prop_set_string(dev, "part-name", "M2S010");
     67    qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);
     68
     69    qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
     70    qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
     71
     72    /*
     73     * CPU clock and peripheral clocks(APB0, APB1)are configurable
     74     * in Libero. CPU clock is divided by APB0 and APB1 divisors for
     75     * peripherals. Emcraft's SoM kit comes with these settings by default.
     76     */
     77    /* This clock doesn't need migration because it is fixed-frequency */
     78    m3clk = clock_new(OBJECT(machine), "m3clk");
     79    clock_set_hz(m3clk, 142 * 1000000);
     80    qdev_connect_clock_in(dev, "m3clk", m3clk);
     81    qdev_prop_set_uint32(dev, "apb0div", 2);
     82    qdev_prop_set_uint32(dev, "apb1div", 2);
     83
     84    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     85
     86    soc = MSF2_SOC(dev);
     87
     88    /* Attach SPI flash to SPI0 controller */
     89    spi_bus = qdev_get_child_bus(dev, "spi0");
     90    spi_flash = qdev_new("s25sl12801");
     91    qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
     92    if (dinfo) {
     93        qdev_prop_set_drive_err(spi_flash, "drive",
     94                                blk_by_legacy_dinfo(dinfo), &error_fatal);
     95    }
     96    qdev_realize_and_unref(spi_flash, spi_bus, &error_fatal);
     97    cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
     98    sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
     99
    100    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
    101                       soc->envm_size);
    102}
    103
    104static void emcraft_sf2_machine_init(MachineClass *mc)
    105{
    106    mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
    107    mc->init = emcraft_sf2_s2s010_init;
    108    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
    109}
    110
    111DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)