cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

sabrelite.c (3760B)

      1/*
      2 * SABRELITE Board System emulation.
      3 *
      4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
      5 *
      6 * This code is licensed under the GPL, version 2 or later.
      7 * See the file `COPYING' in the top level directory.
      8 *
      9 * It (partially) emulates a sabrelite board, with a Freescale
     10 * i.MX6 SoC
     11 */
     12
     13#include "qemu/osdep.h"
     14#include "qapi/error.h"
     15#include "hw/arm/fsl-imx6.h"
     16#include "hw/boards.h"
     17#include "hw/qdev-properties.h"
     18#include "qemu/error-report.h"
     19#include "sysemu/qtest.h"
     20
     21static struct arm_boot_info sabrelite_binfo = {
     22    /* DDR memory start */
     23    .loader_start = FSL_IMX6_MMDC_ADDR,
     24    /* No board ID, we boot from DT tree */
     25    .board_id = -1,
     26};
     27
     28/* No need to do any particular setup for secondary boot */
     29static void sabrelite_write_secondary(ARMCPU *cpu,
     30                                      const struct arm_boot_info *info)
     31{
     32}
     33
     34/* Secondary cores are reset through SRC device */
     35static void sabrelite_reset_secondary(ARMCPU *cpu,
     36                                      const struct arm_boot_info *info)
     37{
     38}
     39
     40static void sabrelite_init(MachineState *machine)
     41{
     42    FslIMX6State *s;
     43
     44    /* Check the amount of memory is compatible with the SOC */
     45    if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
     46        error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
     47                     machine->ram_size, FSL_IMX6_MMDC_SIZE);
     48        exit(1);
     49    }
     50
     51    s = FSL_IMX6(object_new(TYPE_FSL_IMX6));
     52    object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
     53
     54    /* Ethernet PHY address is 6 */
     55    object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal);
     56
     57    qdev_realize(DEVICE(s), NULL, &error_fatal);
     58
     59    memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
     60                                machine->ram);
     61
     62    {
     63        /*
     64         * TODO: Ideally we would expose the chip select and spi bus on the
     65         * SoC object using alias properties; then we would not need to
     66         * directly access the underlying spi device object.
     67         */
     68        /* Add the sst25vf016b NOR FLASH memory to first SPI */
     69        Object *spi_dev;
     70
     71        spi_dev = object_resolve_path_component(OBJECT(s), "spi1");
     72        if (spi_dev) {
     73            SSIBus *spi_bus;
     74
     75            spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
     76            if (spi_bus) {
     77                DeviceState *flash_dev;
     78                qemu_irq cs_line;
     79                DriveInfo *dinfo = drive_get_next(IF_MTD);
     80
     81                flash_dev = qdev_new("sst25vf016b");
     82                if (dinfo) {
     83                    qdev_prop_set_drive_err(flash_dev, "drive",
     84                                            blk_by_legacy_dinfo(dinfo),
     85                                            &error_fatal);
     86                }
     87                qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
     88
     89                cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
     90                qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line);
     91            }
     92        }
     93    }
     94
     95    sabrelite_binfo.ram_size = machine->ram_size;
     96    sabrelite_binfo.nb_cpus = machine->smp.cpus;
     97    sabrelite_binfo.secure_boot = true;
     98    sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
     99    sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
    100
    101    if (!qtest_enabled()) {
    102        arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo);
    103    }
    104}
    105
    106static void sabrelite_machine_init(MachineClass *mc)
    107{
    108    mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex-A9)";
    109    mc->init = sabrelite_init;
    110    mc->max_cpus = FSL_IMX6_NUM_CPUS;
    111    mc->ignore_memory_transaction_failures = true;
    112    mc->default_ram_id = "sabrelite.ram";
    113}
    114
    115DEFINE_MACHINE("sabrelite", sabrelite_machine_init)