cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

via-ac97.c (2812B)

      1/*
      2 * VIA south bridges sound support
      3 *
      4 * This work is licensed under the GNU GPL license version 2 or later.
      5 */
      6
      7/*
      8 * TODO: This is entirely boiler plate just registering empty PCI devices
      9 * with the right ID guests expect, functionality should be added here.
     10 */
     11
     12#include "qemu/osdep.h"
     13#include "hw/isa/vt82c686.h"
     14#include "hw/pci/pci.h"
     15
     16static void via_ac97_realize(PCIDevice *pci_dev, Error **errp)
     17{
     18    pci_set_word(pci_dev->config + PCI_COMMAND,
     19                 PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY);
     20    pci_set_word(pci_dev->config + PCI_STATUS,
     21                 PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_MEDIUM);
     22    pci_set_long(pci_dev->config + PCI_INTERRUPT_PIN, 0x03);
     23}
     24
     25static void via_ac97_class_init(ObjectClass *klass, void *data)
     26{
     27    DeviceClass *dc = DEVICE_CLASS(klass);
     28    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
     29
     30    k->realize = via_ac97_realize;
     31    k->vendor_id = PCI_VENDOR_ID_VIA;
     32    k->device_id = PCI_DEVICE_ID_VIA_AC97;
     33    k->revision = 0x50;
     34    k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
     35    set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
     36    dc->desc = "VIA AC97";
     37    /* Reason: Part of a south bridge chip */
     38    dc->user_creatable = false;
     39}
     40
     41static const TypeInfo via_ac97_info = {
     42    .name          = TYPE_VIA_AC97,
     43    .parent        = TYPE_PCI_DEVICE,
     44    .instance_size = sizeof(PCIDevice),
     45    .class_init    = via_ac97_class_init,
     46    .interfaces = (InterfaceInfo[]) {
     47        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
     48        { },
     49    },
     50};
     51
     52static void via_mc97_realize(PCIDevice *pci_dev, Error **errp)
     53{
     54    pci_set_word(pci_dev->config + PCI_COMMAND,
     55                 PCI_COMMAND_INVALIDATE | PCI_COMMAND_VGA_PALETTE);
     56    pci_set_word(pci_dev->config + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
     57    pci_set_long(pci_dev->config + PCI_INTERRUPT_PIN, 0x03);
     58}
     59
     60static void via_mc97_class_init(ObjectClass *klass, void *data)
     61{
     62    DeviceClass *dc = DEVICE_CLASS(klass);
     63    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
     64
     65    k->realize = via_mc97_realize;
     66    k->vendor_id = PCI_VENDOR_ID_VIA;
     67    k->device_id = PCI_DEVICE_ID_VIA_MC97;
     68    k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
     69    k->revision = 0x30;
     70    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
     71    dc->desc = "VIA MC97";
     72    /* Reason: Part of a south bridge chip */
     73    dc->user_creatable = false;
     74}
     75
     76static const TypeInfo via_mc97_info = {
     77    .name          = TYPE_VIA_MC97,
     78    .parent        = TYPE_PCI_DEVICE,
     79    .instance_size = sizeof(PCIDevice),
     80    .class_init    = via_mc97_class_init,
     81    .interfaces = (InterfaceInfo[]) {
     82        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
     83        { },
     84    },
     85};
     86
     87static void via_ac97_register_types(void)
     88{
     89    type_register_static(&via_ac97_info);
     90    type_register_static(&via_mc97_info);
     91}
     92
     93type_init(via_ac97_register_types)