cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

trace-events (6722B)


      1# See docs/devel/tracing.rst for syntax documentation.
      2
      3# parallel.c
      4parallel_ioport_read(const char *desc, uint16_t addr, uint8_t value) "read [%s] addr 0x%02x val 0x%02x"
      5parallel_ioport_write(const char *desc, uint16_t addr, uint8_t value) "write [%s] addr 0x%02x val 0x%02x"
      6
      7# serial.c
      8serial_read(uint16_t addr, uint8_t value) "read addr 0x%02x val 0x%02x"
      9serial_write(uint16_t addr, uint8_t value) "write addr 0x%02x val 0x%02x"
     10serial_update_parameters(uint64_t baudrate, char parity, int data_bits, int stop_bits) "baudrate=%"PRIu64" parity='%c' data=%d stop=%d"
     11
     12# virtio-serial-bus.c
     13virtio_serial_send_control_event(unsigned int port, uint16_t event, uint16_t value) "port %u, event %u, value %u"
     14virtio_serial_throttle_port(unsigned int port, bool throttle) "port %u, throttle %d"
     15virtio_serial_handle_control_message(uint16_t event, uint16_t value) "event %u, value %u"
     16virtio_serial_handle_control_message_port(unsigned int port) "port %u"
     17
     18# virtio-console.c
     19virtio_console_flush_buf(unsigned int port, size_t len, ssize_t ret) "port %u, in_len %zu, out_len %zd"
     20virtio_console_chr_read(unsigned int port, int size) "port %u, size %d"
     21virtio_console_chr_event(unsigned int port, int event) "port %u, event %d"
     22
     23# goldfish_tty.c
     24goldfish_tty_read(void *dev, unsigned int addr, unsigned int size, uint64_t value) "tty: %p reg: 0x%02x size: %d value: 0x%"PRIx64
     25goldfish_tty_write(void *dev, unsigned int addr, unsigned int size, uint64_t value) "tty: %p reg: 0x%02x size: %d value: 0x%"PRIx64
     26goldfish_tty_can_receive(void *dev, unsigned int available) "tty: %p available: %u"
     27goldfish_tty_receive(void *dev, unsigned int size) "tty: %p size: %u"
     28goldfish_tty_reset(void *dev) "tty: %p"
     29goldfish_tty_realize(void *dev) "tty: %p"
     30goldfish_tty_unrealize(void *dev) "tty: %p"
     31goldfish_tty_instance_init(void *dev) "tty: %p"
     32
     33# grlib_apbuart.c
     34grlib_apbuart_event(int event) "event:%d"
     35grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
     36grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64
     37
     38# escc.c
     39escc_hard_reset(void) "hard reset"
     40escc_soft_reset_chn(char channel) "soft reset channel %c"
     41escc_put_queue(char channel, int b) "channel %c put: 0x%02x"
     42escc_get_queue(char channel, int val) "channel %c get 0x%02x"
     43escc_update_irq(int irq) "IRQ = %d"
     44escc_update_parameters(char channel, int speed, int parity, int data_bits, int stop_bits) "channel %c: speed=%d parity=%c data=%d stop=%d"
     45escc_mem_writeb_ctrl(char channel, uint32_t reg, uint32_t val) "Write channel %c, reg[%d] = 0x%2.2x"
     46escc_mem_writeb_data(char channel, uint32_t val) "Write channel %c, ch %d"
     47escc_mem_readb_ctrl(char channel, uint32_t reg, uint8_t val) "Read channel %c, reg[%d] = 0x%2.2x"
     48escc_mem_readb_data(char channel, uint32_t ret) "Read channel %c, ch %d"
     49escc_serial_receive_byte(char channel, int ch) "channel %c put ch %d"
     50escc_sunkbd_event_in(int ch, const char *name, int down) "QKeyCode 0x%2.2x [%s], down %d"
     51escc_sunkbd_event_out(int ch) "Translated keycode 0x%2.2x"
     52escc_kbd_command(int val) "Command %d"
     53escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=0x%01x"
     54
     55# pl011.c
     56pl011_irq_state(int level) "irq state %d"
     57pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
     58pl011_read_fifo(int read_count) "FIFO read, read_count now %d"
     59pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
     60pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
     61pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
     62pl011_put_fifo_full(void) "FIFO now full, RXFF set"
     63pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
     64
     65# cmsdk-apb-uart.c
     66cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
     67cmsdk_apb_uart_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
     68cmsdk_apb_uart_reset(void) "CMSDK APB UART: reset"
     69cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got character 0x%x from backend"
     70cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend pending"
     71cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backend"
     72cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
     73
     74# nrf51_uart.c
     75nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
     76nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
     77
     78# shakti_uart.c
     79shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
     80shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
     81
     82# exynos4210_uart.c
     83exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
     84exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
     85exynos_uart_irq_raised(uint32_t channel, uint32_t reg) "UART%d: IRQ raised: 0x%08"PRIx32
     86exynos_uart_irq_lowered(uint32_t channel) "UART%d: IRQ lowered"
     87exynos_uart_update_params(uint32_t channel, int speed, uint8_t parity, int data, int stop, uint64_t wordtime) "UART%d: speed: %d, parity: %c, data bits: %d, stop bits: %d wordtime: %"PRId64"ns"
     88exynos_uart_write(uint32_t channel, uint32_t offset, const char *name, uint64_t val) "UART%d: <0x%04x> %s <- 0x%" PRIx64
     89exynos_uart_read(uint32_t channel, uint32_t offset, const char *name, uint64_t val) "UART%d: <0x%04x> %s -> 0x%" PRIx64
     90exynos_uart_rx_fifo_reset(uint32_t channel) "UART%d: Rx FIFO Reset"
     91exynos_uart_tx_fifo_reset(uint32_t channel) "UART%d: Tx FIFO Reset"
     92exynos_uart_tx(uint32_t channel, uint8_t ch) "UART%d: Tx 0x%02"PRIx32
     93exynos_uart_intclr(uint32_t channel, uint32_t reg) "UART%d: interrupts cleared: 0x%08"PRIx32
     94exynos_uart_ro_write(uint32_t channel, const char *name, uint32_t reg) "UART%d: Trying to write into RO register: %s [0x%04"PRIx32"]"
     95exynos_uart_rx(uint32_t channel, uint8_t ch) "UART%d: Rx 0x%02"PRIx32
     96exynos_uart_rx_error(uint32_t channel) "UART%d: Rx error"
     97exynos_uart_wo_read(uint32_t channel, const char *name, uint32_t reg) "UART%d: Trying to read from WO register: %s [0x%04"PRIx32"]"
     98exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size: %d"
     99exynos_uart_channel_error(uint32_t channel) "Wrong UART channel number: %d"
    100exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "UART%d: Rx timeout stat=0x%x intsp=0x%x"
    101
    102# cadence_uart.c
    103cadence_uart_baudrate(unsigned baudrate) "baudrate %u"