cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

i82374.c (4780B)

      1/*
      2 * QEMU Intel 82374 emulation (Enhanced DMA controller)
      3 *
      4 * Copyright (c) 2010 Hervé Poussineau
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#include "qemu/osdep.h"
     26#include "qapi/error.h"
     27#include "qemu/module.h"
     28#include "hw/isa/isa.h"
     29#include "hw/qdev-properties.h"
     30#include "migration/vmstate.h"
     31#include "hw/dma/i8257.h"
     32#include "qom/object.h"
     33
     34#define TYPE_I82374 "i82374"
     35OBJECT_DECLARE_SIMPLE_TYPE(I82374State, I82374)
     36
     37//#define DEBUG_I82374
     38
     39#ifdef DEBUG_I82374
     40#define DPRINTF(fmt, ...) \
     41do { fprintf(stderr, "i82374: " fmt , ## __VA_ARGS__); } while (0)
     42#else
     43#define DPRINTF(fmt, ...) \
     44do {} while (0)
     45#endif
     46#define BADF(fmt, ...) \
     47do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
     48
     49struct I82374State {
     50    ISADevice parent_obj;
     51
     52    uint32_t iobase;
     53    uint8_t commands[8];
     54    PortioList port_list;
     55};
     56
     57static const VMStateDescription vmstate_i82374 = {
     58    .name = "i82374",
     59    .version_id = 0,
     60    .minimum_version_id = 0,
     61    .fields = (VMStateField[]) {
     62        VMSTATE_UINT8_ARRAY(commands, I82374State, 8),
     63        VMSTATE_END_OF_LIST()
     64    },
     65};
     66
     67static uint32_t i82374_read_isr(void *opaque, uint32_t nport)
     68{
     69    uint32_t val = 0;
     70
     71    BADF("%s: %08x\n", __func__, nport);
     72
     73    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
     74    return val;
     75}
     76
     77static void i82374_write_command(void *opaque, uint32_t nport, uint32_t data)
     78{
     79    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
     80
     81    if (data != 0x42) {
     82        /* Not Stop S/G command */
     83        BADF("%s: %08x=%08x\n", __func__, nport, data);
     84    }
     85}
     86
     87static uint32_t i82374_read_status(void *opaque, uint32_t nport)
     88{
     89    uint32_t val = 0;
     90
     91    BADF("%s: %08x\n", __func__, nport);
     92
     93    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
     94    return val;
     95}
     96
     97static void i82374_write_descriptor(void *opaque, uint32_t nport, uint32_t data)
     98{
     99    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
    100
    101    BADF("%s: %08x=%08x\n", __func__, nport, data);
    102}
    103
    104static uint32_t i82374_read_descriptor(void *opaque, uint32_t nport)
    105{
    106    uint32_t val = 0;
    107
    108    BADF("%s: %08x\n", __func__, nport);
    109
    110    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
    111    return val;
    112}
    113
    114static const MemoryRegionPortio i82374_portio_list[] = {
    115    { 0x0A, 1, 1, .read = i82374_read_isr, },
    116    { 0x10, 8, 1, .write = i82374_write_command, },
    117    { 0x18, 8, 1, .read = i82374_read_status, },
    118    { 0x20, 0x20, 1,
    119      .write = i82374_write_descriptor, .read = i82374_read_descriptor, },
    120    PORTIO_END_OF_LIST(),
    121};
    122
    123static void i82374_realize(DeviceState *dev, Error **errp)
    124{
    125    I82374State *s = I82374(dev);
    126    ISABus *isa_bus = isa_bus_from_device(ISA_DEVICE(dev));
    127
    128    if (isa_get_dma(isa_bus, 0)) {
    129        error_setg(errp, "DMA already initialized on ISA bus");
    130        return;
    131    }
    132    i8257_dma_init(isa_bus, true);
    133
    134    portio_list_init(&s->port_list, OBJECT(s), i82374_portio_list, s,
    135                     "i82374");
    136    portio_list_add(&s->port_list, isa_address_space_io(&s->parent_obj),
    137                    s->iobase);
    138
    139    memset(s->commands, 0, sizeof(s->commands));
    140}
    141
    142static Property i82374_properties[] = {
    143    DEFINE_PROP_UINT32("iobase", I82374State, iobase, 0x400),
    144    DEFINE_PROP_END_OF_LIST()
    145};
    146
    147static void i82374_class_init(ObjectClass *klass, void *data)
    148{
    149    DeviceClass *dc = DEVICE_CLASS(klass);
    150    
    151    dc->realize = i82374_realize;
    152    dc->vmsd = &vmstate_i82374;
    153    device_class_set_props(dc, i82374_properties);
    154}
    155
    156static const TypeInfo i82374_info = {
    157    .name  = TYPE_I82374,
    158    .parent = TYPE_ISA_DEVICE,
    159    .instance_size  = sizeof(I82374State),
    160    .class_init = i82374_class_init,
    161};
    162
    163static void i82374_register_types(void)
    164{
    165    type_register_static(&i82374_info);
    166}
    167
    168type_init(i82374_register_types)