cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

rc4030.c (19718B)

      1/*
      2 * QEMU JAZZ RC4030 chipset
      3 *
      4 * Copyright (c) 2007-2013 Hervé Poussineau
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#include "qemu/osdep.h"
     26#include "qemu/units.h"
     27#include "hw/irq.h"
     28#include "hw/mips/mips.h"
     29#include "hw/sysbus.h"
     30#include "migration/vmstate.h"
     31#include "qapi/error.h"
     32#include "qemu/timer.h"
     33#include "qemu/log.h"
     34#include "qemu/module.h"
     35#include "exec/address-spaces.h"
     36#include "trace.h"
     37#include "qom/object.h"
     38
     39/********************************************************/
     40/* rc4030 emulation                                     */
     41
     42typedef struct dma_pagetable_entry {
     43    int32_t frame;
     44    int32_t owner;
     45} QEMU_PACKED dma_pagetable_entry;
     46
     47#define DMA_PAGESIZE    4096
     48#define DMA_REG_ENABLE  1
     49#define DMA_REG_COUNT   2
     50#define DMA_REG_ADDRESS 3
     51
     52#define DMA_FLAG_ENABLE     0x0001
     53#define DMA_FLAG_MEM_TO_DEV 0x0002
     54#define DMA_FLAG_TC_INTR    0x0100
     55#define DMA_FLAG_MEM_INTR   0x0200
     56#define DMA_FLAG_ADDR_INTR  0x0400
     57
     58#define TYPE_RC4030 "rc4030"
     59OBJECT_DECLARE_SIMPLE_TYPE(rc4030State, RC4030)
     60
     61#define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
     62
     63struct rc4030State {
     64
     65    SysBusDevice parent;
     66
     67    uint32_t config; /* 0x0000: RC4030 config register */
     68    uint32_t revision; /* 0x0008: RC4030 Revision register */
     69    uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
     70
     71    /* DMA */
     72    uint32_t dma_regs[8][4];
     73    uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
     74    uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
     75
     76    /* cache */
     77    uint32_t cache_maint; /* 0x0030: Cache Maintenance */
     78    uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
     79    uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
     80    uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
     81    uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
     82    uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
     83
     84    uint32_t nmi_interrupt; /* 0x0200: interrupt source */
     85    uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */
     86    uint32_t nvram_protect; /* 0x0220: NV ram protect register */
     87    uint32_t rem_speed[16];
     88    uint32_t imr_jazz; /* Local bus int enable mask */
     89    uint32_t isr_jazz; /* Local bus int source */
     90
     91    /* timer */
     92    QEMUTimer *periodic_timer;
     93    uint32_t itr; /* Interval timer reload */
     94
     95    qemu_irq timer_irq;
     96    qemu_irq jazz_bus_irq;
     97
     98    /* whole DMA memory region, root of DMA address space */
     99    IOMMUMemoryRegion dma_mr;
    100    AddressSpace dma_as;
    101
    102    MemoryRegion iomem_chipset;
    103    MemoryRegion iomem_jazzio;
    104};
    105
    106static void set_next_tick(rc4030State *s)
    107{
    108    uint32_t tm_hz;
    109    qemu_irq_lower(s->timer_irq);
    110
    111    tm_hz = 1000 / (s->itr + 1);
    112
    113    timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
    114                   NANOSECONDS_PER_SECOND / tm_hz);
    115}
    116
    117/* called for accesses to rc4030 */
    118static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size)
    119{
    120    rc4030State *s = opaque;
    121    uint32_t val;
    122
    123    addr &= 0x3fff;
    124    switch (addr & ~0x3) {
    125    /* Global config register */
    126    case 0x0000:
    127        val = s->config;
    128        break;
    129    /* Revision register */
    130    case 0x0008:
    131        val = s->revision;
    132        break;
    133    /* Invalid Address register */
    134    case 0x0010:
    135        val = s->invalid_address_register;
    136        break;
    137    /* DMA transl. table base */
    138    case 0x0018:
    139        val = s->dma_tl_base;
    140        break;
    141    /* DMA transl. table limit */
    142    case 0x0020:
    143        val = s->dma_tl_limit;
    144        break;
    145    /* Remote Failed Address */
    146    case 0x0038:
    147        val = s->remote_failed_address;
    148        break;
    149    /* Memory Failed Address */
    150    case 0x0040:
    151        val = s->memory_failed_address;
    152        break;
    153    /* I/O Cache Byte Mask */
    154    case 0x0058:
    155        val = s->cache_bmask;
    156        /* HACK */
    157        if (s->cache_bmask == (uint32_t)-1) {
    158            s->cache_bmask = 0;
    159        }
    160        break;
    161    /* Remote Speed Registers */
    162    case 0x0070:
    163    case 0x0078:
    164    case 0x0080:
    165    case 0x0088:
    166    case 0x0090:
    167    case 0x0098:
    168    case 0x00a0:
    169    case 0x00a8:
    170    case 0x00b0:
    171    case 0x00b8:
    172    case 0x00c0:
    173    case 0x00c8:
    174    case 0x00d0:
    175    case 0x00d8:
    176    case 0x00e0:
    177    case 0x00e8:
    178        val = s->rem_speed[(addr - 0x0070) >> 3];
    179        break;
    180    /* DMA channel base address */
    181    case 0x0100:
    182    case 0x0108:
    183    case 0x0110:
    184    case 0x0118:
    185    case 0x0120:
    186    case 0x0128:
    187    case 0x0130:
    188    case 0x0138:
    189    case 0x0140:
    190    case 0x0148:
    191    case 0x0150:
    192    case 0x0158:
    193    case 0x0160:
    194    case 0x0168:
    195    case 0x0170:
    196    case 0x0178:
    197    case 0x0180:
    198    case 0x0188:
    199    case 0x0190:
    200    case 0x0198:
    201    case 0x01a0:
    202    case 0x01a8:
    203    case 0x01b0:
    204    case 0x01b8:
    205    case 0x01c0:
    206    case 0x01c8:
    207    case 0x01d0:
    208    case 0x01d8:
    209    case 0x01e0:
    210    case 0x01e8:
    211    case 0x01f0:
    212    case 0x01f8:
    213        {
    214            int entry = (addr - 0x0100) >> 5;
    215            int idx = (addr & 0x1f) >> 3;
    216            val = s->dma_regs[entry][idx];
    217        }
    218        break;
    219    /* Interrupt source */
    220    case 0x0200:
    221        val = s->nmi_interrupt;
    222        break;
    223    /* Error type */
    224    case 0x0208:
    225        val = 0;
    226        break;
    227    /* Memory refresh rate */
    228    case 0x0210:
    229        val = s->memory_refresh_rate;
    230        break;
    231    /* NV ram protect register */
    232    case 0x0220:
    233        val = s->nvram_protect;
    234        break;
    235    /* Interval timer count */
    236    case 0x0230:
    237        val = 0;
    238        qemu_irq_lower(s->timer_irq);
    239        break;
    240    /* EISA interrupt */
    241    case 0x0238:
    242        val = 7; /* FIXME: should be read from EISA controller */
    243        break;
    244    default:
    245        qemu_log_mask(LOG_GUEST_ERROR,
    246                      "rc4030: invalid read at 0x%x", (int)addr);
    247        val = 0;
    248        break;
    249    }
    250
    251    if ((addr & ~3) != 0x230) {
    252        trace_rc4030_read(addr, val);
    253    }
    254
    255    return val;
    256}
    257
    258static void rc4030_write(void *opaque, hwaddr addr, uint64_t data,
    259                         unsigned int size)
    260{
    261    rc4030State *s = opaque;
    262    uint32_t val = data;
    263    addr &= 0x3fff;
    264
    265    trace_rc4030_write(addr, val);
    266
    267    switch (addr & ~0x3) {
    268    /* Global config register */
    269    case 0x0000:
    270        s->config = val;
    271        break;
    272    /* DMA transl. table base */
    273    case 0x0018:
    274        s->dma_tl_base = val;
    275        break;
    276    /* DMA transl. table limit */
    277    case 0x0020:
    278        s->dma_tl_limit = val;
    279        break;
    280    /* DMA transl. table invalidated */
    281    case 0x0028:
    282        break;
    283    /* Cache Maintenance */
    284    case 0x0030:
    285        s->cache_maint = val;
    286        break;
    287    /* I/O Cache Physical Tag */
    288    case 0x0048:
    289        s->cache_ptag = val;
    290        break;
    291    /* I/O Cache Logical Tag */
    292    case 0x0050:
    293        s->cache_ltag = val;
    294        break;
    295    /* I/O Cache Byte Mask */
    296    case 0x0058:
    297        s->cache_bmask |= val; /* HACK */
    298        break;
    299    /* I/O Cache Buffer Window */
    300    case 0x0060:
    301        /* HACK */
    302        if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
    303            hwaddr dest = s->cache_ptag & ~0x1;
    304            dest += (s->cache_maint & 0x3) << 3;
    305            cpu_physical_memory_write(dest, &val, 4);
    306        }
    307        break;
    308    /* Remote Speed Registers */
    309    case 0x0070:
    310    case 0x0078:
    311    case 0x0080:
    312    case 0x0088:
    313    case 0x0090:
    314    case 0x0098:
    315    case 0x00a0:
    316    case 0x00a8:
    317    case 0x00b0:
    318    case 0x00b8:
    319    case 0x00c0:
    320    case 0x00c8:
    321    case 0x00d0:
    322    case 0x00d8:
    323    case 0x00e0:
    324    case 0x00e8:
    325        s->rem_speed[(addr - 0x0070) >> 3] = val;
    326        break;
    327    /* DMA channel base address */
    328    case 0x0100:
    329    case 0x0108:
    330    case 0x0110:
    331    case 0x0118:
    332    case 0x0120:
    333    case 0x0128:
    334    case 0x0130:
    335    case 0x0138:
    336    case 0x0140:
    337    case 0x0148:
    338    case 0x0150:
    339    case 0x0158:
    340    case 0x0160:
    341    case 0x0168:
    342    case 0x0170:
    343    case 0x0178:
    344    case 0x0180:
    345    case 0x0188:
    346    case 0x0190:
    347    case 0x0198:
    348    case 0x01a0:
    349    case 0x01a8:
    350    case 0x01b0:
    351    case 0x01b8:
    352    case 0x01c0:
    353    case 0x01c8:
    354    case 0x01d0:
    355    case 0x01d8:
    356    case 0x01e0:
    357    case 0x01e8:
    358    case 0x01f0:
    359    case 0x01f8:
    360        {
    361            int entry = (addr - 0x0100) >> 5;
    362            int idx = (addr & 0x1f) >> 3;
    363            s->dma_regs[entry][idx] = val;
    364        }
    365        break;
    366    /* Memory refresh rate */
    367    case 0x0210:
    368        s->memory_refresh_rate = val;
    369        break;
    370    /* Interval timer reload */
    371    case 0x0228:
    372        s->itr = val & 0x01FF;
    373        qemu_irq_lower(s->timer_irq);
    374        set_next_tick(s);
    375        break;
    376    /* EISA interrupt */
    377    case 0x0238:
    378        break;
    379    default:
    380        qemu_log_mask(LOG_GUEST_ERROR,
    381                      "rc4030: invalid write of 0x%02x at 0x%x",
    382                      val, (int)addr);
    383        break;
    384    }
    385}
    386
    387static const MemoryRegionOps rc4030_ops = {
    388    .read = rc4030_read,
    389    .write = rc4030_write,
    390    .impl.min_access_size = 4,
    391    .impl.max_access_size = 4,
    392    .endianness = DEVICE_NATIVE_ENDIAN,
    393};
    394
    395static void update_jazz_irq(rc4030State *s)
    396{
    397    uint16_t pending;
    398
    399    pending = s->isr_jazz & s->imr_jazz;
    400
    401    if (pending != 0) {
    402        qemu_irq_raise(s->jazz_bus_irq);
    403    } else {
    404        qemu_irq_lower(s->jazz_bus_irq);
    405    }
    406}
    407
    408static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
    409{
    410    rc4030State *s = opaque;
    411
    412    if (level) {
    413        s->isr_jazz |= 1 << irq;
    414    } else {
    415        s->isr_jazz &= ~(1 << irq);
    416    }
    417
    418    update_jazz_irq(s);
    419}
    420
    421static void rc4030_periodic_timer(void *opaque)
    422{
    423    rc4030State *s = opaque;
    424
    425    set_next_tick(s);
    426    qemu_irq_raise(s->timer_irq);
    427}
    428
    429static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size)
    430{
    431    rc4030State *s = opaque;
    432    uint32_t val;
    433    uint32_t irq;
    434    addr &= 0xfff;
    435
    436    switch (addr) {
    437    /* Local bus int source */
    438    case 0x00: {
    439        uint32_t pending = s->isr_jazz & s->imr_jazz;
    440        val = 0;
    441        irq = 0;
    442        while (pending) {
    443            if (pending & 1) {
    444                val = (irq + 1) << 2;
    445                break;
    446            }
    447            irq++;
    448            pending >>= 1;
    449        }
    450        break;
    451    }
    452    /* Local bus int enable mask */
    453    case 0x02:
    454        val = s->imr_jazz;
    455        break;
    456    default:
    457        qemu_log_mask(LOG_GUEST_ERROR,
    458                      "rc4030/jazzio: invalid read at 0x%x", (int)addr);
    459        val = 0;
    460        break;
    461    }
    462
    463    trace_jazzio_read(addr, val);
    464
    465    return val;
    466}
    467
    468static void jazzio_write(void *opaque, hwaddr addr, uint64_t data,
    469                         unsigned int size)
    470{
    471    rc4030State *s = opaque;
    472    uint32_t val = data;
    473    addr &= 0xfff;
    474
    475    trace_jazzio_write(addr, val);
    476
    477    switch (addr) {
    478    /* Local bus int enable mask */
    479    case 0x02:
    480        s->imr_jazz = val;
    481        update_jazz_irq(s);
    482        break;
    483    default:
    484        qemu_log_mask(LOG_GUEST_ERROR,
    485                      "rc4030/jazzio: invalid write of 0x%02x at 0x%x",
    486                      val, (int)addr);
    487        break;
    488    }
    489}
    490
    491static const MemoryRegionOps jazzio_ops = {
    492    .read = jazzio_read,
    493    .write = jazzio_write,
    494    .impl.min_access_size = 2,
    495    .impl.max_access_size = 2,
    496    .endianness = DEVICE_NATIVE_ENDIAN,
    497};
    498
    499static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
    500                                          IOMMUAccessFlags flag, int iommu_idx)
    501{
    502    rc4030State *s = container_of(iommu, rc4030State, dma_mr);
    503    IOMMUTLBEntry ret = {
    504        .target_as = &address_space_memory,
    505        .iova = addr & ~(DMA_PAGESIZE - 1),
    506        .translated_addr = 0,
    507        .addr_mask = DMA_PAGESIZE - 1,
    508        .perm = IOMMU_NONE,
    509    };
    510    uint64_t i, entry_address;
    511    dma_pagetable_entry entry;
    512
    513    i = addr / DMA_PAGESIZE;
    514    if (i < s->dma_tl_limit / sizeof(entry)) {
    515        entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
    516        if (address_space_read(ret.target_as, entry_address,
    517                               MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry))
    518                == MEMTX_OK) {
    519            ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
    520            ret.perm = IOMMU_RW;
    521        }
    522    }
    523
    524    return ret;
    525}
    526
    527static void rc4030_reset(DeviceState *dev)
    528{
    529    rc4030State *s = RC4030(dev);
    530    int i;
    531
    532    s->config = 0x410; /* some boards seem to accept 0x104 too */
    533    s->revision = 1;
    534    s->invalid_address_register = 0;
    535
    536    memset(s->dma_regs, 0, sizeof(s->dma_regs));
    537
    538    s->remote_failed_address = s->memory_failed_address = 0;
    539    s->cache_maint = 0;
    540    s->cache_ptag = s->cache_ltag = 0;
    541    s->cache_bmask = 0;
    542
    543    s->memory_refresh_rate = 0x18186;
    544    s->nvram_protect = 7;
    545    for (i = 0; i < 15; i++) {
    546        s->rem_speed[i] = 7;
    547    }
    548    s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
    549    s->isr_jazz = 0;
    550
    551    s->itr = 0;
    552
    553    qemu_irq_lower(s->timer_irq);
    554    qemu_irq_lower(s->jazz_bus_irq);
    555}
    556
    557static int rc4030_post_load(void *opaque, int version_id)
    558{
    559    rc4030State *s = opaque;
    560
    561    set_next_tick(s);
    562    update_jazz_irq(s);
    563
    564    return 0;
    565}
    566
    567static const VMStateDescription vmstate_rc4030 = {
    568    .name = "rc4030",
    569    .version_id = 3,
    570    .post_load = rc4030_post_load,
    571    .fields = (VMStateField []) {
    572        VMSTATE_UINT32(config, rc4030State),
    573        VMSTATE_UINT32(invalid_address_register, rc4030State),
    574        VMSTATE_UINT32_2DARRAY(dma_regs, rc4030State, 8, 4),
    575        VMSTATE_UINT32(dma_tl_base, rc4030State),
    576        VMSTATE_UINT32(dma_tl_limit, rc4030State),
    577        VMSTATE_UINT32(cache_maint, rc4030State),
    578        VMSTATE_UINT32(remote_failed_address, rc4030State),
    579        VMSTATE_UINT32(memory_failed_address, rc4030State),
    580        VMSTATE_UINT32(cache_ptag, rc4030State),
    581        VMSTATE_UINT32(cache_ltag, rc4030State),
    582        VMSTATE_UINT32(cache_bmask, rc4030State),
    583        VMSTATE_UINT32(memory_refresh_rate, rc4030State),
    584        VMSTATE_UINT32(nvram_protect, rc4030State),
    585        VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16),
    586        VMSTATE_UINT32(imr_jazz, rc4030State),
    587        VMSTATE_UINT32(isr_jazz, rc4030State),
    588        VMSTATE_UINT32(itr, rc4030State),
    589        VMSTATE_END_OF_LIST()
    590    }
    591};
    592
    593static void rc4030_do_dma(void *opaque, int n, uint8_t *buf,
    594                          int len, bool is_write)
    595{
    596    rc4030State *s = opaque;
    597    hwaddr dma_addr;
    598    int dev_to_mem;
    599
    600    s->dma_regs[n][DMA_REG_ENABLE] &=
    601           ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
    602
    603    /* Check DMA channel consistency */
    604    dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
    605    if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
    606        (is_write != dev_to_mem)) {
    607        s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
    608        s->nmi_interrupt |= 1 << n;
    609        return;
    610    }
    611
    612    /* Get start address and len */
    613    if (len > s->dma_regs[n][DMA_REG_COUNT]) {
    614        len = s->dma_regs[n][DMA_REG_COUNT];
    615    }
    616    dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
    617
    618    /* Read/write data at right place */
    619    address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED,
    620                     buf, len, is_write);
    621
    622    s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
    623    s->dma_regs[n][DMA_REG_COUNT] -= len;
    624}
    625
    626struct rc4030DMAState {
    627    void *opaque;
    628    int n;
    629};
    630
    631void rc4030_dma_read(void *dma, uint8_t *buf, int len)
    632{
    633    rc4030_dma s = dma;
    634    rc4030_do_dma(s->opaque, s->n, buf, len, false);
    635}
    636
    637void rc4030_dma_write(void *dma, uint8_t *buf, int len)
    638{
    639    rc4030_dma s = dma;
    640    rc4030_do_dma(s->opaque, s->n, buf, len, true);
    641}
    642
    643static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
    644{
    645    rc4030_dma *s;
    646    struct rc4030DMAState *p;
    647    int i;
    648
    649    s = (rc4030_dma *)g_new0(rc4030_dma, n);
    650    p = (struct rc4030DMAState *)g_new0(struct rc4030DMAState, n);
    651    for (i = 0; i < n; i++) {
    652        p->opaque = opaque;
    653        p->n = i;
    654        s[i] = p;
    655        p++;
    656    }
    657    return s;
    658}
    659
    660static void rc4030_initfn(Object *obj)
    661{
    662    DeviceState *dev = DEVICE(obj);
    663    rc4030State *s = RC4030(obj);
    664    SysBusDevice *sysbus = SYS_BUS_DEVICE(obj);
    665
    666    qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16);
    667
    668    sysbus_init_irq(sysbus, &s->timer_irq);
    669    sysbus_init_irq(sysbus, &s->jazz_bus_irq);
    670
    671    sysbus_init_mmio(sysbus, &s->iomem_chipset);
    672    sysbus_init_mmio(sysbus, &s->iomem_jazzio);
    673}
    674
    675static void rc4030_realize(DeviceState *dev, Error **errp)
    676{
    677    rc4030State *s = RC4030(dev);
    678    Object *o = OBJECT(dev);
    679
    680    s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
    681                                     rc4030_periodic_timer, s);
    682
    683    memory_region_init_io(&s->iomem_chipset, o, &rc4030_ops, s,
    684                          "rc4030.chipset", 0x300);
    685    memory_region_init_io(&s->iomem_jazzio, o, &jazzio_ops, s,
    686                          "rc4030.jazzio", 0x00001000);
    687
    688    memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr),
    689                             TYPE_RC4030_IOMMU_MEMORY_REGION,
    690                             o, "rc4030.dma", 4 * GiB);
    691    address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma");
    692}
    693
    694static void rc4030_unrealize(DeviceState *dev)
    695{
    696    rc4030State *s = RC4030(dev);
    697
    698    timer_free(s->periodic_timer);
    699
    700    address_space_destroy(&s->dma_as);
    701    object_unparent(OBJECT(&s->dma_mr));
    702}
    703
    704static void rc4030_class_init(ObjectClass *klass, void *class_data)
    705{
    706    DeviceClass *dc = DEVICE_CLASS(klass);
    707
    708    dc->realize = rc4030_realize;
    709    dc->unrealize = rc4030_unrealize;
    710    dc->reset = rc4030_reset;
    711    dc->vmsd = &vmstate_rc4030;
    712}
    713
    714static const TypeInfo rc4030_info = {
    715    .name = TYPE_RC4030,
    716    .parent = TYPE_SYS_BUS_DEVICE,
    717    .instance_size = sizeof(rc4030State),
    718    .instance_init = rc4030_initfn,
    719    .class_init = rc4030_class_init,
    720};
    721
    722static void rc4030_iommu_memory_region_class_init(ObjectClass *klass,
    723                                                  void *data)
    724{
    725    IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
    726
    727    imrc->translate = rc4030_dma_translate;
    728}
    729
    730static const TypeInfo rc4030_iommu_memory_region_info = {
    731    .parent = TYPE_IOMMU_MEMORY_REGION,
    732    .name = TYPE_RC4030_IOMMU_MEMORY_REGION,
    733    .class_init = rc4030_iommu_memory_region_class_init,
    734};
    735
    736static void rc4030_register_types(void)
    737{
    738    type_register_static(&rc4030_info);
    739    type_register_static(&rc4030_iommu_memory_region_info);
    740}
    741
    742type_init(rc4030_register_types)
    743
    744DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr)
    745{
    746    DeviceState *dev;
    747
    748    dev = qdev_new(TYPE_RC4030);
    749    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    750
    751    *dmas = rc4030_allocate_dmas(dev, 4);
    752    *dma_mr = &RC4030(dev)->dma_mr;
    753    return dev;
    754}