cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

sparc32_dma.c (14079B)


      1/*
      2 * QEMU Sparc32 DMA controller emulation
      3 *
      4 * Copyright (c) 2006 Fabrice Bellard
      5 *
      6 * Modifications:
      7 *  2010-Feb-14 Artyom Tarasenko : reworked irq generation
      8 *
      9 * Permission is hereby granted, free of charge, to any person obtaining a copy
     10 * of this software and associated documentation files (the "Software"), to deal
     11 * in the Software without restriction, including without limitation the rights
     12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     13 * copies of the Software, and to permit persons to whom the Software is
     14 * furnished to do so, subject to the following conditions:
     15 *
     16 * The above copyright notice and this permission notice shall be included in
     17 * all copies or substantial portions of the Software.
     18 *
     19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     25 * THE SOFTWARE.
     26 */
     27
     28#include "qemu/osdep.h"
     29#include "hw/irq.h"
     30#include "hw/qdev-properties.h"
     31#include "hw/sparc/sparc32_dma.h"
     32#include "hw/sparc/sun4m_iommu.h"
     33#include "hw/sysbus.h"
     34#include "migration/vmstate.h"
     35#include "sysemu/dma.h"
     36#include "qapi/error.h"
     37#include "qemu/module.h"
     38#include "trace.h"
     39
     40/*
     41 * This is the DMA controller part of chip STP2000 (Master I/O), also
     42 * produced as NCR89C100. See
     43 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
     44 * and
     45 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
     46 */
     47
     48#define DMA_SIZE (4 * sizeof(uint32_t))
     49/* We need the mask, because one instance of the device is not page
     50   aligned (ledma, start address 0x0010) */
     51#define DMA_MASK (DMA_SIZE - 1)
     52/* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
     53#define DMA_ETH_SIZE (8 * sizeof(uint32_t))
     54#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
     55
     56#define DMA_VER 0xa0000000
     57#define DMA_INTR 1
     58#define DMA_INTREN 0x10
     59#define DMA_WRITE_MEM 0x100
     60#define DMA_EN 0x200
     61#define DMA_LOADED 0x04000000
     62#define DMA_DRAIN_FIFO 0x40
     63#define DMA_RESET 0x80
     64
     65/* XXX SCSI and ethernet should have different read-only bit masks */
     66#define DMA_CSR_RO_MASK 0xfe000007
     67
     68enum {
     69    GPIO_RESET = 0,
     70    GPIO_DMA,
     71};
     72
     73/* Note: on sparc, the lance 16 bit bus is swapped */
     74void ledma_memory_read(void *opaque, hwaddr addr,
     75                       uint8_t *buf, int len, int do_bswap)
     76{
     77    DMADeviceState *s = opaque;
     78    IOMMUState *is = (IOMMUState *)s->iommu;
     79    int i;
     80
     81    addr |= s->dmaregs[3];
     82    trace_ledma_memory_read(addr, len);
     83    if (do_bswap) {
     84        dma_memory_read(&is->iommu_as, addr, buf, len);
     85    } else {
     86        addr &= ~1;
     87        len &= ~1;
     88        dma_memory_read(&is->iommu_as, addr, buf, len);
     89        for(i = 0; i < len; i += 2) {
     90            bswap16s((uint16_t *)(buf + i));
     91        }
     92    }
     93}
     94
     95void ledma_memory_write(void *opaque, hwaddr addr,
     96                        uint8_t *buf, int len, int do_bswap)
     97{
     98    DMADeviceState *s = opaque;
     99    IOMMUState *is = (IOMMUState *)s->iommu;
    100    int l, i;
    101    uint16_t tmp_buf[32];
    102
    103    addr |= s->dmaregs[3];
    104    trace_ledma_memory_write(addr, len);
    105    if (do_bswap) {
    106        dma_memory_write(&is->iommu_as, addr, buf, len);
    107    } else {
    108        addr &= ~1;
    109        len &= ~1;
    110        while (len > 0) {
    111            l = len;
    112            if (l > sizeof(tmp_buf))
    113                l = sizeof(tmp_buf);
    114            for(i = 0; i < l; i += 2) {
    115                tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
    116            }
    117            dma_memory_write(&is->iommu_as, addr, tmp_buf, l);
    118            len -= l;
    119            buf += l;
    120            addr += l;
    121        }
    122    }
    123}
    124
    125static void dma_set_irq(void *opaque, int irq, int level)
    126{
    127    DMADeviceState *s = opaque;
    128    if (level) {
    129        s->dmaregs[0] |= DMA_INTR;
    130        if (s->dmaregs[0] & DMA_INTREN) {
    131            trace_sparc32_dma_set_irq_raise();
    132            qemu_irq_raise(s->irq);
    133        }
    134    } else {
    135        if (s->dmaregs[0] & DMA_INTR) {
    136            s->dmaregs[0] &= ~DMA_INTR;
    137            if (s->dmaregs[0] & DMA_INTREN) {
    138                trace_sparc32_dma_set_irq_lower();
    139                qemu_irq_lower(s->irq);
    140            }
    141        }
    142    }
    143}
    144
    145void espdma_memory_read(void *opaque, uint8_t *buf, int len)
    146{
    147    DMADeviceState *s = opaque;
    148    IOMMUState *is = (IOMMUState *)s->iommu;
    149
    150    trace_espdma_memory_read(s->dmaregs[1], len);
    151    dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len);
    152    s->dmaregs[1] += len;
    153}
    154
    155void espdma_memory_write(void *opaque, uint8_t *buf, int len)
    156{
    157    DMADeviceState *s = opaque;
    158    IOMMUState *is = (IOMMUState *)s->iommu;
    159
    160    trace_espdma_memory_write(s->dmaregs[1], len);
    161    dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len);
    162    s->dmaregs[1] += len;
    163}
    164
    165static uint64_t dma_mem_read(void *opaque, hwaddr addr,
    166                             unsigned size)
    167{
    168    DMADeviceState *s = opaque;
    169    uint32_t saddr;
    170
    171    saddr = (addr & DMA_MASK) >> 2;
    172    trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
    173    return s->dmaregs[saddr];
    174}
    175
    176static void dma_mem_write(void *opaque, hwaddr addr,
    177                          uint64_t val, unsigned size)
    178{
    179    DMADeviceState *s = opaque;
    180    uint32_t saddr;
    181
    182    saddr = (addr & DMA_MASK) >> 2;
    183    trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
    184    switch (saddr) {
    185    case 0:
    186        if (val & DMA_INTREN) {
    187            if (s->dmaregs[0] & DMA_INTR) {
    188                trace_sparc32_dma_set_irq_raise();
    189                qemu_irq_raise(s->irq);
    190            }
    191        } else {
    192            if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
    193                trace_sparc32_dma_set_irq_lower();
    194                qemu_irq_lower(s->irq);
    195            }
    196        }
    197        if (val & DMA_RESET) {
    198            qemu_irq_raise(s->gpio[GPIO_RESET]);
    199            qemu_irq_lower(s->gpio[GPIO_RESET]);
    200        } else if (val & DMA_DRAIN_FIFO) {
    201            val &= ~DMA_DRAIN_FIFO;
    202        } else if (val == 0)
    203            val = DMA_DRAIN_FIFO;
    204
    205        if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
    206            trace_sparc32_dma_enable_raise();
    207            qemu_irq_raise(s->gpio[GPIO_DMA]);
    208        } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
    209            trace_sparc32_dma_enable_lower();
    210            qemu_irq_lower(s->gpio[GPIO_DMA]);
    211        }
    212
    213        val &= ~DMA_CSR_RO_MASK;
    214        val |= DMA_VER;
    215        s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
    216        break;
    217    case 1:
    218        s->dmaregs[0] |= DMA_LOADED;
    219        /* fall through */
    220    default:
    221        s->dmaregs[saddr] = val;
    222        break;
    223    }
    224}
    225
    226static const MemoryRegionOps dma_mem_ops = {
    227    .read = dma_mem_read,
    228    .write = dma_mem_write,
    229    .endianness = DEVICE_NATIVE_ENDIAN,
    230    .valid = {
    231        .min_access_size = 4,
    232        .max_access_size = 4,
    233    },
    234};
    235
    236static void sparc32_dma_device_reset(DeviceState *d)
    237{
    238    DMADeviceState *s = SPARC32_DMA_DEVICE(d);
    239
    240    memset(s->dmaregs, 0, DMA_SIZE);
    241    s->dmaregs[0] = DMA_VER;
    242}
    243
    244static const VMStateDescription vmstate_sparc32_dma_device = {
    245    .name ="sparc32_dma",
    246    .version_id = 2,
    247    .minimum_version_id = 2,
    248    .fields = (VMStateField[]) {
    249        VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
    250        VMSTATE_END_OF_LIST()
    251    }
    252};
    253
    254static void sparc32_dma_device_init(Object *obj)
    255{
    256    DeviceState *dev = DEVICE(obj);
    257    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
    258    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    259
    260    sysbus_init_irq(sbd, &s->irq);
    261
    262    sysbus_init_mmio(sbd, &s->iomem);
    263
    264    object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
    265                             (Object **) &s->iommu,
    266                             qdev_prop_allow_set_link_before_realize,
    267                             0);
    268
    269    qdev_init_gpio_in(dev, dma_set_irq, 1);
    270    qdev_init_gpio_out(dev, s->gpio, 2);
    271}
    272
    273static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
    274{
    275    DeviceClass *dc = DEVICE_CLASS(klass);
    276
    277    dc->reset = sparc32_dma_device_reset;
    278    dc->vmsd = &vmstate_sparc32_dma_device;
    279}
    280
    281static const TypeInfo sparc32_dma_device_info = {
    282    .name          = TYPE_SPARC32_DMA_DEVICE,
    283    .parent        = TYPE_SYS_BUS_DEVICE,
    284    .abstract      = true,
    285    .instance_size = sizeof(DMADeviceState),
    286    .instance_init = sparc32_dma_device_init,
    287    .class_init    = sparc32_dma_device_class_init,
    288};
    289
    290static void sparc32_espdma_device_init(Object *obj)
    291{
    292    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
    293    ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(obj);
    294
    295    memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
    296                          "espdma-mmio", DMA_SIZE);
    297
    298    object_initialize_child(obj, "esp", &es->esp, TYPE_SYSBUS_ESP);
    299}
    300
    301static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
    302{
    303    ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev);
    304    SysBusESPState *sysbus = SYSBUS_ESP(&es->esp);
    305    ESPState *esp = &sysbus->esp;
    306
    307    esp->dma_memory_read = espdma_memory_read;
    308    esp->dma_memory_write = espdma_memory_write;
    309    esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
    310    sysbus->it_shift = 2;
    311    esp->dma_enabled = 1;
    312    sysbus_realize(SYS_BUS_DEVICE(sysbus), &error_fatal);
    313}
    314
    315static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
    316{
    317    DeviceClass *dc = DEVICE_CLASS(klass);
    318
    319    dc->realize = sparc32_espdma_device_realize;
    320}
    321
    322static const TypeInfo sparc32_espdma_device_info = {
    323    .name          = TYPE_SPARC32_ESPDMA_DEVICE,
    324    .parent        = TYPE_SPARC32_DMA_DEVICE,
    325    .instance_size = sizeof(ESPDMADeviceState),
    326    .instance_init = sparc32_espdma_device_init,
    327    .class_init    = sparc32_espdma_device_class_init,
    328};
    329
    330static void sparc32_ledma_device_init(Object *obj)
    331{
    332    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
    333    LEDMADeviceState *ls = SPARC32_LEDMA_DEVICE(obj);
    334
    335    memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
    336                          "ledma-mmio", DMA_SIZE);
    337
    338    object_initialize_child(obj, "lance", &ls->lance, TYPE_LANCE);
    339}
    340
    341static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
    342{
    343    LEDMADeviceState *s = SPARC32_LEDMA_DEVICE(dev);
    344    SysBusPCNetState *lance = SYSBUS_PCNET(&s->lance);
    345
    346    object_property_set_link(OBJECT(lance), "dma", OBJECT(dev), &error_abort);
    347    sysbus_realize(SYS_BUS_DEVICE(lance), &error_fatal);
    348}
    349
    350static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
    351{
    352    DeviceClass *dc = DEVICE_CLASS(klass);
    353
    354    dc->realize = sparc32_ledma_device_realize;
    355}
    356
    357static const TypeInfo sparc32_ledma_device_info = {
    358    .name          = TYPE_SPARC32_LEDMA_DEVICE,
    359    .parent        = TYPE_SPARC32_DMA_DEVICE,
    360    .instance_size = sizeof(LEDMADeviceState),
    361    .instance_init = sparc32_ledma_device_init,
    362    .class_init    = sparc32_ledma_device_class_init,
    363};
    364
    365static void sparc32_dma_realize(DeviceState *dev, Error **errp)
    366{
    367    SPARC32DMAState *s = SPARC32_DMA(dev);
    368    DeviceState *espdma, *esp, *ledma, *lance;
    369    SysBusDevice *sbd;
    370    Object *iommu;
    371
    372    iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
    373    if (!iommu) {
    374        error_setg(errp, "unable to locate sun4m IOMMU device");
    375        return;
    376    }
    377
    378    espdma = DEVICE(&s->espdma);
    379    object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort);
    380    sysbus_realize(SYS_BUS_DEVICE(espdma), &error_fatal);
    381
    382    esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
    383    sbd = SYS_BUS_DEVICE(esp);
    384    sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
    385    qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
    386    qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
    387
    388    sbd = SYS_BUS_DEVICE(espdma);
    389    memory_region_add_subregion(&s->dmamem, 0x0,
    390                                sysbus_mmio_get_region(sbd, 0));
    391
    392    ledma = DEVICE(&s->ledma);
    393    object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort);
    394    sysbus_realize(SYS_BUS_DEVICE(ledma), &error_fatal);
    395
    396    lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
    397    sbd = SYS_BUS_DEVICE(lance);
    398    sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
    399    qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
    400
    401    sbd = SYS_BUS_DEVICE(ledma);
    402    memory_region_add_subregion(&s->dmamem, 0x10,
    403                                sysbus_mmio_get_region(sbd, 0));
    404
    405    /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */
    406    memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",
    407                             sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);
    408    memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);
    409}
    410
    411static void sparc32_dma_init(Object *obj)
    412{
    413    SPARC32DMAState *s = SPARC32_DMA(obj);
    414    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    415
    416    memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
    417    sysbus_init_mmio(sbd, &s->dmamem);
    418
    419    object_initialize_child(obj, "espdma", &s->espdma,
    420                            TYPE_SPARC32_ESPDMA_DEVICE);
    421    object_initialize_child(obj, "ledma", &s->ledma,
    422                            TYPE_SPARC32_LEDMA_DEVICE);
    423}
    424
    425static void sparc32_dma_class_init(ObjectClass *klass, void *data)
    426{
    427    DeviceClass *dc = DEVICE_CLASS(klass);
    428
    429    dc->realize = sparc32_dma_realize;
    430}
    431
    432static const TypeInfo sparc32_dma_info = {
    433    .name          = TYPE_SPARC32_DMA,
    434    .parent        = TYPE_SYS_BUS_DEVICE,
    435    .instance_size = sizeof(SPARC32DMAState),
    436    .instance_init = sparc32_dma_init,
    437    .class_init    = sparc32_dma_class_init,
    438};
    439
    440
    441static void sparc32_dma_register_types(void)
    442{
    443    type_register_static(&sparc32_dma_device_info);
    444    type_register_static(&sparc32_espdma_device_info);
    445    type_register_static(&sparc32_ledma_device_info);
    446    type_register_static(&sparc32_dma_info);
    447}
    448
    449type_init(sparc32_dma_register_types)