cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

realview_gic.c (2495B)

      1/*
      2 * ARM RealView Emulation Baseboard Interrupt Controller
      3 *
      4 * Copyright (c) 2006-2007 CodeSourcery.
      5 * Written by Paul Brook
      6 *
      7 * This code is licensed under the GPL.
      8 */
      9
     10#include "qemu/osdep.h"
     11#include "qapi/error.h"
     12#include "qemu/module.h"
     13#include "hw/intc/realview_gic.h"
     14#include "hw/irq.h"
     15#include "hw/qdev-properties.h"
     16
     17static void realview_gic_set_irq(void *opaque, int irq, int level)
     18{
     19    RealViewGICState *s = (RealViewGICState *)opaque;
     20
     21    qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
     22}
     23
     24static void realview_gic_realize(DeviceState *dev, Error **errp)
     25{
     26    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     27    RealViewGICState *s = REALVIEW_GIC(dev);
     28    SysBusDevice *busdev;
     29    /* The GICs on the RealView boards have a fixed nonconfigurable
     30     * number of interrupt lines, so we don't need to expose this as
     31     * a qdev property.
     32     */
     33    int numirq = 96;
     34
     35    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq);
     36    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
     37        return;
     38    }
     39    busdev = SYS_BUS_DEVICE(&s->gic);
     40
     41    /* Pass through outbound IRQ lines from the GIC */
     42    sysbus_pass_irq(sbd, busdev);
     43
     44    /* Pass through inbound GPIO lines to the GIC */
     45    qdev_init_gpio_in(dev, realview_gic_set_irq, numirq - 32);
     46
     47    memory_region_add_subregion(&s->container, 0,
     48                                sysbus_mmio_get_region(busdev, 1));
     49    memory_region_add_subregion(&s->container, 0x1000,
     50                                sysbus_mmio_get_region(busdev, 0));
     51}
     52
     53static void realview_gic_init(Object *obj)
     54{
     55    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     56    RealViewGICState *s = REALVIEW_GIC(obj);
     57
     58    memory_region_init(&s->container, OBJECT(s),
     59                       "realview-gic-container", 0x2000);
     60    sysbus_init_mmio(sbd, &s->container);
     61
     62    object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
     63    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", 1);
     64}
     65
     66static void realview_gic_class_init(ObjectClass *oc, void *data)
     67{
     68    DeviceClass *dc = DEVICE_CLASS(oc);
     69
     70    dc->realize = realview_gic_realize;
     71}
     72
     73static const TypeInfo realview_gic_info = {
     74    .name          = TYPE_REALVIEW_GIC,
     75    .parent        = TYPE_SYS_BUS_DEVICE,
     76    .instance_size = sizeof(RealViewGICState),
     77    .instance_init = realview_gic_init,
     78    .class_init    = realview_gic_class_init,
     79};
     80
     81static void realview_gic_register_types(void)
     82{
     83    type_register_static(&realview_gic_info);
     84}
     85
     86type_init(realview_gic_register_types)