cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

i82378.c (4068B)

      1/*
      2 * QEMU Intel i82378 emulation (PCI to ISA bridge)
      3 *
      4 * Copyright (c) 2010-2011 Hervé Poussineau
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#include "qemu/osdep.h"
     21#include "hw/pci/pci.h"
     22#include "hw/irq.h"
     23#include "hw/intc/i8259.h"
     24#include "hw/timer/i8254.h"
     25#include "migration/vmstate.h"
     26#include "hw/audio/pcspk.h"
     27#include "qom/object.h"
     28
     29#define TYPE_I82378 "i82378"
     30OBJECT_DECLARE_SIMPLE_TYPE(I82378State, I82378)
     31
     32struct I82378State {
     33    PCIDevice parent_obj;
     34
     35    qemu_irq out[2];
     36    qemu_irq *i8259;
     37    MemoryRegion io;
     38};
     39
     40static const VMStateDescription vmstate_i82378 = {
     41    .name = "pci-i82378",
     42    .version_id = 0,
     43    .minimum_version_id = 0,
     44    .fields = (VMStateField[]) {
     45        VMSTATE_PCI_DEVICE(parent_obj, I82378State),
     46        VMSTATE_END_OF_LIST()
     47    },
     48};
     49
     50static void i82378_request_out0_irq(void *opaque, int irq, int level)
     51{
     52    I82378State *s = opaque;
     53    qemu_set_irq(s->out[0], level);
     54}
     55
     56static void i82378_request_pic_irq(void *opaque, int irq, int level)
     57{
     58    DeviceState *dev = opaque;
     59    I82378State *s = I82378(dev);
     60
     61    qemu_set_irq(s->i8259[irq], level);
     62}
     63
     64static void i82378_realize(PCIDevice *pci, Error **errp)
     65{
     66    DeviceState *dev = DEVICE(pci);
     67    I82378State *s = I82378(dev);
     68    uint8_t *pci_conf;
     69    ISABus *isabus;
     70    ISADevice *pit;
     71
     72    pci_conf = pci->config;
     73    pci_set_word(pci_conf + PCI_COMMAND,
     74                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
     75    pci_set_word(pci_conf + PCI_STATUS,
     76                 PCI_STATUS_DEVSEL_MEDIUM);
     77
     78    pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */
     79
     80    isabus = isa_bus_new(dev, get_system_memory(),
     81                         pci_address_space_io(pci), errp);
     82    if (!isabus) {
     83        return;
     84    }
     85
     86    /* This device has:
     87       2 82C59 (irq)
     88       1 82C54 (pit)
     89       2 82C37 (dma)
     90       NMI
     91       Utility Bus Support Registers
     92
     93       All devices accept byte access only, except timer
     94     */
     95
     96    /* 2 82C59 (irq) */
     97    s->i8259 = i8259_init(isabus,
     98                          qemu_allocate_irq(i82378_request_out0_irq, s, 0));
     99    isa_bus_irqs(isabus, s->i8259);
    100
    101    /* 1 82C54 (pit) */
    102    pit = i8254_pit_init(isabus, 0x40, 0, NULL);
    103
    104    /* speaker */
    105    pcspk_init(isa_new(TYPE_PC_SPEAKER), isabus, pit);
    106
    107    /* 2 82C37 (dma) */
    108    isa_create_simple(isabus, "i82374");
    109}
    110
    111static void i82378_init(Object *obj)
    112{
    113    DeviceState *dev = DEVICE(obj);
    114    I82378State *s = I82378(obj);
    115
    116    qdev_init_gpio_out(dev, s->out, 1);
    117    qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
    118}
    119
    120static void i82378_class_init(ObjectClass *klass, void *data)
    121{
    122    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    123    DeviceClass *dc = DEVICE_CLASS(klass);
    124
    125    k->realize = i82378_realize;
    126    k->vendor_id = PCI_VENDOR_ID_INTEL;
    127    k->device_id = PCI_DEVICE_ID_INTEL_82378;
    128    k->revision = 0x03;
    129    k->class_id = PCI_CLASS_BRIDGE_ISA;
    130    dc->vmsd = &vmstate_i82378;
    131    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
    132}
    133
    134static const TypeInfo i82378_type_info = {
    135    .name = TYPE_I82378,
    136    .parent = TYPE_PCI_DEVICE,
    137    .instance_size = sizeof(I82378State),
    138    .instance_init = i82378_init,
    139    .class_init = i82378_class_init,
    140    .interfaces = (InterfaceInfo[]) {
    141        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
    142        { },
    143    },
    144};
    145
    146static void i82378_register_types(void)
    147{
    148    type_register_static(&i82378_type_info);
    149}
    150
    151type_init(i82378_register_types)