gt64xxx_pci.c (40694B)
1/* 2 * QEMU GT64120 PCI host 3 * 4 * Copyright (c) 2006,2007 Aurelien Jarno 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "qemu/osdep.h" 26#include "qapi/error.h" 27#include "qemu/units.h" 28#include "qemu/log.h" 29#include "hw/mips/mips.h" 30#include "hw/pci/pci.h" 31#include "hw/pci/pci_host.h" 32#include "hw/southbridge/piix.h" 33#include "migration/vmstate.h" 34#include "hw/intc/i8259.h" 35#include "hw/irq.h" 36#include "trace.h" 37#include "qom/object.h" 38 39#define GT_REGS (0x1000 >> 2) 40 41/* CPU Configuration */ 42#define GT_CPU (0x000 >> 2) 43#define GT_MULTI (0x120 >> 2) 44 45/* CPU Address Decode */ 46#define GT_SCS10LD (0x008 >> 2) 47#define GT_SCS10HD (0x010 >> 2) 48#define GT_SCS32LD (0x018 >> 2) 49#define GT_SCS32HD (0x020 >> 2) 50#define GT_CS20LD (0x028 >> 2) 51#define GT_CS20HD (0x030 >> 2) 52#define GT_CS3BOOTLD (0x038 >> 2) 53#define GT_CS3BOOTHD (0x040 >> 2) 54#define GT_PCI0IOLD (0x048 >> 2) 55#define GT_PCI0IOHD (0x050 >> 2) 56#define GT_PCI0M0LD (0x058 >> 2) 57#define GT_PCI0M0HD (0x060 >> 2) 58#define GT_PCI0M1LD (0x080 >> 2) 59#define GT_PCI0M1HD (0x088 >> 2) 60#define GT_PCI1IOLD (0x090 >> 2) 61#define GT_PCI1IOHD (0x098 >> 2) 62#define GT_PCI1M0LD (0x0a0 >> 2) 63#define GT_PCI1M0HD (0x0a8 >> 2) 64#define GT_PCI1M1LD (0x0b0 >> 2) 65#define GT_PCI1M1HD (0x0b8 >> 2) 66#define GT_ISD (0x068 >> 2) 67 68#define GT_SCS10AR (0x0d0 >> 2) 69#define GT_SCS32AR (0x0d8 >> 2) 70#define GT_CS20R (0x0e0 >> 2) 71#define GT_CS3BOOTR (0x0e8 >> 2) 72 73#define GT_PCI0IOREMAP (0x0f0 >> 2) 74#define GT_PCI0M0REMAP (0x0f8 >> 2) 75#define GT_PCI0M1REMAP (0x100 >> 2) 76#define GT_PCI1IOREMAP (0x108 >> 2) 77#define GT_PCI1M0REMAP (0x110 >> 2) 78#define GT_PCI1M1REMAP (0x118 >> 2) 79 80/* CPU Error Report */ 81#define GT_CPUERR_ADDRLO (0x070 >> 2) 82#define GT_CPUERR_ADDRHI (0x078 >> 2) 83#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ 84#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ 85#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ 86 87/* CPU Sync Barrier */ 88#define GT_PCI0SYNC (0x0c0 >> 2) 89#define GT_PCI1SYNC (0x0c8 >> 2) 90 91/* SDRAM and Device Address Decode */ 92#define GT_SCS0LD (0x400 >> 2) 93#define GT_SCS0HD (0x404 >> 2) 94#define GT_SCS1LD (0x408 >> 2) 95#define GT_SCS1HD (0x40c >> 2) 96#define GT_SCS2LD (0x410 >> 2) 97#define GT_SCS2HD (0x414 >> 2) 98#define GT_SCS3LD (0x418 >> 2) 99#define GT_SCS3HD (0x41c >> 2) 100#define GT_CS0LD (0x420 >> 2) 101#define GT_CS0HD (0x424 >> 2) 102#define GT_CS1LD (0x428 >> 2) 103#define GT_CS1HD (0x42c >> 2) 104#define GT_CS2LD (0x430 >> 2) 105#define GT_CS2HD (0x434 >> 2) 106#define GT_CS3LD (0x438 >> 2) 107#define GT_CS3HD (0x43c >> 2) 108#define GT_BOOTLD (0x440 >> 2) 109#define GT_BOOTHD (0x444 >> 2) 110#define GT_ADERR (0x470 >> 2) 111 112/* SDRAM Configuration */ 113#define GT_SDRAM_CFG (0x448 >> 2) 114#define GT_SDRAM_OPMODE (0x474 >> 2) 115#define GT_SDRAM_BM (0x478 >> 2) 116#define GT_SDRAM_ADDRDECODE (0x47c >> 2) 117 118/* SDRAM Parameters */ 119#define GT_SDRAM_B0 (0x44c >> 2) 120#define GT_SDRAM_B1 (0x450 >> 2) 121#define GT_SDRAM_B2 (0x454 >> 2) 122#define GT_SDRAM_B3 (0x458 >> 2) 123 124/* Device Parameters */ 125#define GT_DEV_B0 (0x45c >> 2) 126#define GT_DEV_B1 (0x460 >> 2) 127#define GT_DEV_B2 (0x464 >> 2) 128#define GT_DEV_B3 (0x468 >> 2) 129#define GT_DEV_BOOT (0x46c >> 2) 130 131/* ECC */ 132#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ 133#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ 134#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ 135#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ 136#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ 137 138/* DMA Record */ 139#define GT_DMA0_CNT (0x800 >> 2) 140#define GT_DMA1_CNT (0x804 >> 2) 141#define GT_DMA2_CNT (0x808 >> 2) 142#define GT_DMA3_CNT (0x80c >> 2) 143#define GT_DMA0_SA (0x810 >> 2) 144#define GT_DMA1_SA (0x814 >> 2) 145#define GT_DMA2_SA (0x818 >> 2) 146#define GT_DMA3_SA (0x81c >> 2) 147#define GT_DMA0_DA (0x820 >> 2) 148#define GT_DMA1_DA (0x824 >> 2) 149#define GT_DMA2_DA (0x828 >> 2) 150#define GT_DMA3_DA (0x82c >> 2) 151#define GT_DMA0_NEXT (0x830 >> 2) 152#define GT_DMA1_NEXT (0x834 >> 2) 153#define GT_DMA2_NEXT (0x838 >> 2) 154#define GT_DMA3_NEXT (0x83c >> 2) 155#define GT_DMA0_CUR (0x870 >> 2) 156#define GT_DMA1_CUR (0x874 >> 2) 157#define GT_DMA2_CUR (0x878 >> 2) 158#define GT_DMA3_CUR (0x87c >> 2) 159 160/* DMA Channel Control */ 161#define GT_DMA0_CTRL (0x840 >> 2) 162#define GT_DMA1_CTRL (0x844 >> 2) 163#define GT_DMA2_CTRL (0x848 >> 2) 164#define GT_DMA3_CTRL (0x84c >> 2) 165 166/* DMA Arbiter */ 167#define GT_DMA_ARB (0x860 >> 2) 168 169/* Timer/Counter */ 170#define GT_TC0 (0x850 >> 2) 171#define GT_TC1 (0x854 >> 2) 172#define GT_TC2 (0x858 >> 2) 173#define GT_TC3 (0x85c >> 2) 174#define GT_TC_CONTROL (0x864 >> 2) 175 176/* PCI Internal */ 177#define GT_PCI0_CMD (0xc00 >> 2) 178#define GT_PCI0_TOR (0xc04 >> 2) 179#define GT_PCI0_BS_SCS10 (0xc08 >> 2) 180#define GT_PCI0_BS_SCS32 (0xc0c >> 2) 181#define GT_PCI0_BS_CS20 (0xc10 >> 2) 182#define GT_PCI0_BS_CS3BT (0xc14 >> 2) 183#define GT_PCI1_IACK (0xc30 >> 2) 184#define GT_PCI0_IACK (0xc34 >> 2) 185#define GT_PCI0_BARE (0xc3c >> 2) 186#define GT_PCI0_PREFMBR (0xc40 >> 2) 187#define GT_PCI0_SCS10_BAR (0xc48 >> 2) 188#define GT_PCI0_SCS32_BAR (0xc4c >> 2) 189#define GT_PCI0_CS20_BAR (0xc50 >> 2) 190#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) 191#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) 192#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) 193#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) 194#define GT_PCI1_CMD (0xc80 >> 2) 195#define GT_PCI1_TOR (0xc84 >> 2) 196#define GT_PCI1_BS_SCS10 (0xc88 >> 2) 197#define GT_PCI1_BS_SCS32 (0xc8c >> 2) 198#define GT_PCI1_BS_CS20 (0xc90 >> 2) 199#define GT_PCI1_BS_CS3BT (0xc94 >> 2) 200#define GT_PCI1_BARE (0xcbc >> 2) 201#define GT_PCI1_PREFMBR (0xcc0 >> 2) 202#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) 203#define GT_PCI1_SCS32_BAR (0xccc >> 2) 204#define GT_PCI1_CS20_BAR (0xcd0 >> 2) 205#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) 206#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) 207#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) 208#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) 209#define GT_PCI1_CFGADDR (0xcf0 >> 2) 210#define GT_PCI1_CFGDATA (0xcf4 >> 2) 211#define GT_PCI0_CFGADDR (0xcf8 >> 2) 212#define GT_PCI0_CFGDATA (0xcfc >> 2) 213 214/* Interrupts */ 215#define GT_INTRCAUSE (0xc18 >> 2) 216#define GT_INTRMASK (0xc1c >> 2) 217#define GT_PCI0_ICMASK (0xc24 >> 2) 218#define GT_PCI0_SERR0MASK (0xc28 >> 2) 219#define GT_CPU_INTSEL (0xc70 >> 2) 220#define GT_PCI0_INTSEL (0xc74 >> 2) 221#define GT_HINTRCAUSE (0xc98 >> 2) 222#define GT_HINTRMASK (0xc9c >> 2) 223#define GT_PCI0_HICMASK (0xca4 >> 2) 224#define GT_PCI1_SERR1MASK (0xca8 >> 2) 225 226#define PCI_MAPPING_ENTRY(regname) \ 227 hwaddr regname ##_start; \ 228 hwaddr regname ##_length; \ 229 MemoryRegion regname ##_mem 230 231#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" 232 233OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE) 234 235struct GT64120State { 236 PCIHostState parent_obj; 237 238 uint32_t regs[GT_REGS]; 239 PCI_MAPPING_ENTRY(PCI0IO); 240 PCI_MAPPING_ENTRY(PCI0M0); 241 PCI_MAPPING_ENTRY(PCI0M1); 242 PCI_MAPPING_ENTRY(ISD); 243 MemoryRegion pci0_mem; 244 AddressSpace pci0_mem_as; 245}; 246 247/* Adjust range to avoid touching space which isn't mappable via PCI */ 248/* 249 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 250 * 0x1fc00000 - 0x1fd00000 251 */ 252static void check_reserved_space(hwaddr *start, hwaddr *length) 253{ 254 hwaddr begin = *start; 255 hwaddr end = *start + *length; 256 257 if (end >= 0x1e000000LL && end < 0x1f100000LL) { 258 end = 0x1e000000LL; 259 } 260 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) { 261 begin = 0x1f100000LL; 262 } 263 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) { 264 end = 0x1fc00000LL; 265 } 266 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) { 267 begin = 0x1fd00000LL; 268 } 269 /* XXX: This is broken when a reserved range splits the requested range */ 270 if (end >= 0x1f100000LL && begin < 0x1e000000LL) { 271 end = 0x1e000000LL; 272 } 273 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) { 274 end = 0x1fc00000LL; 275 } 276 277 *start = begin; 278 *length = end - begin; 279} 280 281static void gt64120_isd_mapping(GT64120State *s) 282{ 283 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */ 284 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull; 285 hwaddr length = 0x1000; 286 287 if (s->ISD_length) { 288 memory_region_del_subregion(get_system_memory(), &s->ISD_mem); 289 } 290 check_reserved_space(&start, &length); 291 length = 0x1000; 292 /* Map new address */ 293 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start); 294 s->ISD_start = start; 295 s->ISD_length = length; 296 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); 297} 298 299static void gt64120_pci_mapping(GT64120State *s) 300{ 301 /* Update PCI0IO mapping */ 302 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) { 303 /* Unmap old IO address */ 304 if (s->PCI0IO_length) { 305 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); 306 object_unparent(OBJECT(&s->PCI0IO_mem)); 307 } 308 /* Map new IO address */ 309 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; 310 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - 311 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; 312 if (s->PCI0IO_length) { 313 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io", 314 get_system_io(), 0, s->PCI0IO_length); 315 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, 316 &s->PCI0IO_mem); 317 } 318 } 319 320 /* Update PCI0M0 mapping */ 321 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) { 322 /* Unmap old MEM address */ 323 if (s->PCI0M0_length) { 324 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem); 325 object_unparent(OBJECT(&s->PCI0M0_mem)); 326 } 327 /* Map new mem address */ 328 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21; 329 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) - 330 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21; 331 if (s->PCI0M0_length) { 332 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0", 333 &s->pci0_mem, s->PCI0M0_start, 334 s->PCI0M0_length); 335 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start, 336 &s->PCI0M0_mem); 337 } 338 } 339 340 /* Update PCI0M1 mapping */ 341 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) { 342 /* Unmap old MEM address */ 343 if (s->PCI0M1_length) { 344 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem); 345 object_unparent(OBJECT(&s->PCI0M1_mem)); 346 } 347 /* Map new mem address */ 348 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21; 349 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) - 350 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21; 351 if (s->PCI0M1_length) { 352 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1", 353 &s->pci0_mem, s->PCI0M1_start, 354 s->PCI0M1_length); 355 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start, 356 &s->PCI0M1_mem); 357 } 358 } 359} 360 361static int gt64120_post_load(void *opaque, int version_id) 362{ 363 GT64120State *s = opaque; 364 365 gt64120_isd_mapping(s); 366 gt64120_pci_mapping(s); 367 368 return 0; 369} 370 371static const VMStateDescription vmstate_gt64120 = { 372 .name = "gt64120", 373 .version_id = 1, 374 .minimum_version_id = 1, 375 .post_load = gt64120_post_load, 376 .fields = (VMStateField[]) { 377 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS), 378 VMSTATE_END_OF_LIST() 379 } 380}; 381 382static void gt64120_writel(void *opaque, hwaddr addr, 383 uint64_t val, unsigned size) 384{ 385 GT64120State *s = opaque; 386 PCIHostState *phb = PCI_HOST_BRIDGE(s); 387 uint32_t saddr = addr >> 2; 388 389 trace_gt64120_write(addr, val); 390 if (!(s->regs[GT_CPU] & 0x00001000)) { 391 val = bswap32(val); 392 } 393 394 switch (saddr) { 395 396 /* CPU Configuration */ 397 case GT_CPU: 398 s->regs[GT_CPU] = val; 399 break; 400 case GT_MULTI: 401 /* Read-only register as only one GT64xxx is present on the CPU bus */ 402 break; 403 404 /* CPU Address Decode */ 405 case GT_PCI0IOLD: 406 s->regs[GT_PCI0IOLD] = val & 0x00007fff; 407 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; 408 gt64120_pci_mapping(s); 409 break; 410 case GT_PCI0M0LD: 411 s->regs[GT_PCI0M0LD] = val & 0x00007fff; 412 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; 413 gt64120_pci_mapping(s); 414 break; 415 case GT_PCI0M1LD: 416 s->regs[GT_PCI0M1LD] = val & 0x00007fff; 417 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; 418 gt64120_pci_mapping(s); 419 break; 420 case GT_PCI1IOLD: 421 s->regs[GT_PCI1IOLD] = val & 0x00007fff; 422 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; 423 break; 424 case GT_PCI1M0LD: 425 s->regs[GT_PCI1M0LD] = val & 0x00007fff; 426 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; 427 break; 428 case GT_PCI1M1LD: 429 s->regs[GT_PCI1M1LD] = val & 0x00007fff; 430 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; 431 break; 432 case GT_PCI0M0HD: 433 case GT_PCI0M1HD: 434 case GT_PCI0IOHD: 435 s->regs[saddr] = val & 0x0000007f; 436 gt64120_pci_mapping(s); 437 break; 438 case GT_PCI1IOHD: 439 case GT_PCI1M0HD: 440 case GT_PCI1M1HD: 441 s->regs[saddr] = val & 0x0000007f; 442 break; 443 case GT_ISD: 444 s->regs[saddr] = val & 0x00007fff; 445 gt64120_isd_mapping(s); 446 break; 447 448 case GT_PCI0IOREMAP: 449 case GT_PCI0M0REMAP: 450 case GT_PCI0M1REMAP: 451 case GT_PCI1IOREMAP: 452 case GT_PCI1M0REMAP: 453 case GT_PCI1M1REMAP: 454 s->regs[saddr] = val & 0x000007ff; 455 break; 456 457 /* CPU Error Report */ 458 case GT_CPUERR_ADDRLO: 459 case GT_CPUERR_ADDRHI: 460 case GT_CPUERR_DATALO: 461 case GT_CPUERR_DATAHI: 462 case GT_CPUERR_PARITY: 463 /* Read-only registers, do nothing */ 464 qemu_log_mask(LOG_GUEST_ERROR, 465 "gt64120: Read-only register write " 466 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 467 saddr << 2, size, size << 1, val); 468 break; 469 470 /* CPU Sync Barrier */ 471 case GT_PCI0SYNC: 472 case GT_PCI1SYNC: 473 /* Read-only registers, do nothing */ 474 qemu_log_mask(LOG_GUEST_ERROR, 475 "gt64120: Read-only register write " 476 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 477 saddr << 2, size, size << 1, val); 478 break; 479 480 /* SDRAM and Device Address Decode */ 481 case GT_SCS0LD: 482 case GT_SCS0HD: 483 case GT_SCS1LD: 484 case GT_SCS1HD: 485 case GT_SCS2LD: 486 case GT_SCS2HD: 487 case GT_SCS3LD: 488 case GT_SCS3HD: 489 case GT_CS0LD: 490 case GT_CS0HD: 491 case GT_CS1LD: 492 case GT_CS1HD: 493 case GT_CS2LD: 494 case GT_CS2HD: 495 case GT_CS3LD: 496 case GT_CS3HD: 497 case GT_BOOTLD: 498 case GT_BOOTHD: 499 case GT_ADERR: 500 /* SDRAM Configuration */ 501 case GT_SDRAM_CFG: 502 case GT_SDRAM_OPMODE: 503 case GT_SDRAM_BM: 504 case GT_SDRAM_ADDRDECODE: 505 /* Accept and ignore SDRAM interleave configuration */ 506 s->regs[saddr] = val; 507 break; 508 509 /* Device Parameters */ 510 case GT_DEV_B0: 511 case GT_DEV_B1: 512 case GT_DEV_B2: 513 case GT_DEV_B3: 514 case GT_DEV_BOOT: 515 /* Not implemented */ 516 qemu_log_mask(LOG_UNIMP, 517 "gt64120: Unimplemented device register write " 518 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 519 saddr << 2, size, size << 1, val); 520 break; 521 522 /* ECC */ 523 case GT_ECC_ERRDATALO: 524 case GT_ECC_ERRDATAHI: 525 case GT_ECC_MEM: 526 case GT_ECC_CALC: 527 case GT_ECC_ERRADDR: 528 /* Read-only registers, do nothing */ 529 qemu_log_mask(LOG_GUEST_ERROR, 530 "gt64120: Read-only register write " 531 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 532 saddr << 2, size, size << 1, val); 533 break; 534 535 /* DMA Record */ 536 case GT_DMA0_CNT: 537 case GT_DMA1_CNT: 538 case GT_DMA2_CNT: 539 case GT_DMA3_CNT: 540 case GT_DMA0_SA: 541 case GT_DMA1_SA: 542 case GT_DMA2_SA: 543 case GT_DMA3_SA: 544 case GT_DMA0_DA: 545 case GT_DMA1_DA: 546 case GT_DMA2_DA: 547 case GT_DMA3_DA: 548 case GT_DMA0_NEXT: 549 case GT_DMA1_NEXT: 550 case GT_DMA2_NEXT: 551 case GT_DMA3_NEXT: 552 case GT_DMA0_CUR: 553 case GT_DMA1_CUR: 554 case GT_DMA2_CUR: 555 case GT_DMA3_CUR: 556 557 /* DMA Channel Control */ 558 case GT_DMA0_CTRL: 559 case GT_DMA1_CTRL: 560 case GT_DMA2_CTRL: 561 case GT_DMA3_CTRL: 562 563 /* DMA Arbiter */ 564 case GT_DMA_ARB: 565 /* Not implemented */ 566 qemu_log_mask(LOG_UNIMP, 567 "gt64120: Unimplemented DMA register write " 568 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 569 saddr << 2, size, size << 1, val); 570 break; 571 572 /* Timer/Counter */ 573 case GT_TC0: 574 case GT_TC1: 575 case GT_TC2: 576 case GT_TC3: 577 case GT_TC_CONTROL: 578 /* Not implemented */ 579 qemu_log_mask(LOG_UNIMP, 580 "gt64120: Unimplemented timer register write " 581 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 582 saddr << 2, size, size << 1, val); 583 break; 584 585 /* PCI Internal */ 586 case GT_PCI0_CMD: 587 case GT_PCI1_CMD: 588 s->regs[saddr] = val & 0x0401fc0f; 589 break; 590 case GT_PCI0_TOR: 591 case GT_PCI0_BS_SCS10: 592 case GT_PCI0_BS_SCS32: 593 case GT_PCI0_BS_CS20: 594 case GT_PCI0_BS_CS3BT: 595 case GT_PCI1_IACK: 596 case GT_PCI0_IACK: 597 case GT_PCI0_BARE: 598 case GT_PCI0_PREFMBR: 599 case GT_PCI0_SCS10_BAR: 600 case GT_PCI0_SCS32_BAR: 601 case GT_PCI0_CS20_BAR: 602 case GT_PCI0_CS3BT_BAR: 603 case GT_PCI0_SSCS10_BAR: 604 case GT_PCI0_SSCS32_BAR: 605 case GT_PCI0_SCS3BT_BAR: 606 case GT_PCI1_TOR: 607 case GT_PCI1_BS_SCS10: 608 case GT_PCI1_BS_SCS32: 609 case GT_PCI1_BS_CS20: 610 case GT_PCI1_BS_CS3BT: 611 case GT_PCI1_BARE: 612 case GT_PCI1_PREFMBR: 613 case GT_PCI1_SCS10_BAR: 614 case GT_PCI1_SCS32_BAR: 615 case GT_PCI1_CS20_BAR: 616 case GT_PCI1_CS3BT_BAR: 617 case GT_PCI1_SSCS10_BAR: 618 case GT_PCI1_SSCS32_BAR: 619 case GT_PCI1_SCS3BT_BAR: 620 case GT_PCI1_CFGADDR: 621 case GT_PCI1_CFGDATA: 622 /* not implemented */ 623 qemu_log_mask(LOG_UNIMP, 624 "gt64120: Unimplemented PCI register write " 625 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 626 saddr << 2, size, size << 1, val); 627 break; 628 case GT_PCI0_CFGADDR: 629 phb->config_reg = val & 0x80fffffc; 630 break; 631 case GT_PCI0_CFGDATA: 632 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { 633 val = bswap32(val); 634 } 635 if (phb->config_reg & (1u << 31)) { 636 pci_data_write(phb->bus, phb->config_reg, val, 4); 637 } 638 break; 639 640 /* Interrupts */ 641 case GT_INTRCAUSE: 642 /* not really implemented */ 643 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); 644 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); 645 trace_gt64120_write_intreg("INTRCAUSE", size, val); 646 break; 647 case GT_INTRMASK: 648 s->regs[saddr] = val & 0x3c3ffffe; 649 trace_gt64120_write_intreg("INTRMASK", size, val); 650 break; 651 case GT_PCI0_ICMASK: 652 s->regs[saddr] = val & 0x03fffffe; 653 trace_gt64120_write_intreg("ICMASK", size, val); 654 break; 655 case GT_PCI0_SERR0MASK: 656 s->regs[saddr] = val & 0x0000003f; 657 trace_gt64120_write_intreg("SERR0MASK", size, val); 658 break; 659 660 /* Reserved when only PCI_0 is configured. */ 661 case GT_HINTRCAUSE: 662 case GT_CPU_INTSEL: 663 case GT_PCI0_INTSEL: 664 case GT_HINTRMASK: 665 case GT_PCI0_HICMASK: 666 case GT_PCI1_SERR1MASK: 667 /* not implemented */ 668 break; 669 670 /* SDRAM Parameters */ 671 case GT_SDRAM_B0: 672 case GT_SDRAM_B1: 673 case GT_SDRAM_B2: 674 case GT_SDRAM_B3: 675 /* 676 * We don't simulate electrical parameters of the SDRAM. 677 * Accept, but ignore the values. 678 */ 679 s->regs[saddr] = val; 680 break; 681 682 default: 683 qemu_log_mask(LOG_GUEST_ERROR, 684 "gt64120: Illegal register write " 685 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", 686 saddr << 2, size, size << 1, val); 687 break; 688 } 689} 690 691static uint64_t gt64120_readl(void *opaque, 692 hwaddr addr, unsigned size) 693{ 694 GT64120State *s = opaque; 695 PCIHostState *phb = PCI_HOST_BRIDGE(s); 696 uint32_t val; 697 uint32_t saddr = addr >> 2; 698 699 switch (saddr) { 700 701 /* CPU Configuration */ 702 case GT_MULTI: 703 /* 704 * Only one GT64xxx is present on the CPU bus, return 705 * the initial value. 706 */ 707 val = s->regs[saddr]; 708 break; 709 710 /* CPU Error Report */ 711 case GT_CPUERR_ADDRLO: 712 case GT_CPUERR_ADDRHI: 713 case GT_CPUERR_DATALO: 714 case GT_CPUERR_DATAHI: 715 case GT_CPUERR_PARITY: 716 /* Emulated memory has no error, always return the initial values. */ 717 val = s->regs[saddr]; 718 break; 719 720 /* CPU Sync Barrier */ 721 case GT_PCI0SYNC: 722 case GT_PCI1SYNC: 723 /* 724 * Reading those register should empty all FIFO on the PCI 725 * bus, which are not emulated. The return value should be 726 * a random value that should be ignored. 727 */ 728 val = 0xc000ffee; 729 break; 730 731 /* ECC */ 732 case GT_ECC_ERRDATALO: 733 case GT_ECC_ERRDATAHI: 734 case GT_ECC_MEM: 735 case GT_ECC_CALC: 736 case GT_ECC_ERRADDR: 737 /* Emulated memory has no error, always return the initial values. */ 738 val = s->regs[saddr]; 739 break; 740 741 case GT_CPU: 742 case GT_SCS10LD: 743 case GT_SCS10HD: 744 case GT_SCS32LD: 745 case GT_SCS32HD: 746 case GT_CS20LD: 747 case GT_CS20HD: 748 case GT_CS3BOOTLD: 749 case GT_CS3BOOTHD: 750 case GT_SCS10AR: 751 case GT_SCS32AR: 752 case GT_CS20R: 753 case GT_CS3BOOTR: 754 case GT_PCI0IOLD: 755 case GT_PCI0M0LD: 756 case GT_PCI0M1LD: 757 case GT_PCI1IOLD: 758 case GT_PCI1M0LD: 759 case GT_PCI1M1LD: 760 case GT_PCI0IOHD: 761 case GT_PCI0M0HD: 762 case GT_PCI0M1HD: 763 case GT_PCI1IOHD: 764 case GT_PCI1M0HD: 765 case GT_PCI1M1HD: 766 case GT_PCI0IOREMAP: 767 case GT_PCI0M0REMAP: 768 case GT_PCI0M1REMAP: 769 case GT_PCI1IOREMAP: 770 case GT_PCI1M0REMAP: 771 case GT_PCI1M1REMAP: 772 case GT_ISD: 773 val = s->regs[saddr]; 774 break; 775 case GT_PCI0_IACK: 776 /* Read the IRQ number */ 777 val = pic_read_irq(isa_pic); 778 break; 779 780 /* SDRAM and Device Address Decode */ 781 case GT_SCS0LD: 782 case GT_SCS0HD: 783 case GT_SCS1LD: 784 case GT_SCS1HD: 785 case GT_SCS2LD: 786 case GT_SCS2HD: 787 case GT_SCS3LD: 788 case GT_SCS3HD: 789 case GT_CS0LD: 790 case GT_CS0HD: 791 case GT_CS1LD: 792 case GT_CS1HD: 793 case GT_CS2LD: 794 case GT_CS2HD: 795 case GT_CS3LD: 796 case GT_CS3HD: 797 case GT_BOOTLD: 798 case GT_BOOTHD: 799 case GT_ADERR: 800 val = s->regs[saddr]; 801 break; 802 803 /* SDRAM Configuration */ 804 case GT_SDRAM_CFG: 805 case GT_SDRAM_OPMODE: 806 case GT_SDRAM_BM: 807 case GT_SDRAM_ADDRDECODE: 808 val = s->regs[saddr]; 809 break; 810 811 /* SDRAM Parameters */ 812 case GT_SDRAM_B0: 813 case GT_SDRAM_B1: 814 case GT_SDRAM_B2: 815 case GT_SDRAM_B3: 816 /* 817 * We don't simulate electrical parameters of the SDRAM. 818 * Just return the last written value. 819 */ 820 val = s->regs[saddr]; 821 break; 822 823 /* Device Parameters */ 824 case GT_DEV_B0: 825 case GT_DEV_B1: 826 case GT_DEV_B2: 827 case GT_DEV_B3: 828 case GT_DEV_BOOT: 829 val = s->regs[saddr]; 830 break; 831 832 /* DMA Record */ 833 case GT_DMA0_CNT: 834 case GT_DMA1_CNT: 835 case GT_DMA2_CNT: 836 case GT_DMA3_CNT: 837 case GT_DMA0_SA: 838 case GT_DMA1_SA: 839 case GT_DMA2_SA: 840 case GT_DMA3_SA: 841 case GT_DMA0_DA: 842 case GT_DMA1_DA: 843 case GT_DMA2_DA: 844 case GT_DMA3_DA: 845 case GT_DMA0_NEXT: 846 case GT_DMA1_NEXT: 847 case GT_DMA2_NEXT: 848 case GT_DMA3_NEXT: 849 case GT_DMA0_CUR: 850 case GT_DMA1_CUR: 851 case GT_DMA2_CUR: 852 case GT_DMA3_CUR: 853 val = s->regs[saddr]; 854 break; 855 856 /* DMA Channel Control */ 857 case GT_DMA0_CTRL: 858 case GT_DMA1_CTRL: 859 case GT_DMA2_CTRL: 860 case GT_DMA3_CTRL: 861 val = s->regs[saddr]; 862 break; 863 864 /* DMA Arbiter */ 865 case GT_DMA_ARB: 866 val = s->regs[saddr]; 867 break; 868 869 /* Timer/Counter */ 870 case GT_TC0: 871 case GT_TC1: 872 case GT_TC2: 873 case GT_TC3: 874 case GT_TC_CONTROL: 875 val = s->regs[saddr]; 876 break; 877 878 /* PCI Internal */ 879 case GT_PCI0_CFGADDR: 880 val = phb->config_reg; 881 break; 882 case GT_PCI0_CFGDATA: 883 if (!(phb->config_reg & (1 << 31))) { 884 val = 0xffffffff; 885 } else { 886 val = pci_data_read(phb->bus, phb->config_reg, 4); 887 } 888 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { 889 val = bswap32(val); 890 } 891 break; 892 893 case GT_PCI0_CMD: 894 case GT_PCI0_TOR: 895 case GT_PCI0_BS_SCS10: 896 case GT_PCI0_BS_SCS32: 897 case GT_PCI0_BS_CS20: 898 case GT_PCI0_BS_CS3BT: 899 case GT_PCI1_IACK: 900 case GT_PCI0_BARE: 901 case GT_PCI0_PREFMBR: 902 case GT_PCI0_SCS10_BAR: 903 case GT_PCI0_SCS32_BAR: 904 case GT_PCI0_CS20_BAR: 905 case GT_PCI0_CS3BT_BAR: 906 case GT_PCI0_SSCS10_BAR: 907 case GT_PCI0_SSCS32_BAR: 908 case GT_PCI0_SCS3BT_BAR: 909 case GT_PCI1_CMD: 910 case GT_PCI1_TOR: 911 case GT_PCI1_BS_SCS10: 912 case GT_PCI1_BS_SCS32: 913 case GT_PCI1_BS_CS20: 914 case GT_PCI1_BS_CS3BT: 915 case GT_PCI1_BARE: 916 case GT_PCI1_PREFMBR: 917 case GT_PCI1_SCS10_BAR: 918 case GT_PCI1_SCS32_BAR: 919 case GT_PCI1_CS20_BAR: 920 case GT_PCI1_CS3BT_BAR: 921 case GT_PCI1_SSCS10_BAR: 922 case GT_PCI1_SSCS32_BAR: 923 case GT_PCI1_SCS3BT_BAR: 924 case GT_PCI1_CFGADDR: 925 case GT_PCI1_CFGDATA: 926 val = s->regs[saddr]; 927 break; 928 929 /* Interrupts */ 930 case GT_INTRCAUSE: 931 val = s->regs[saddr]; 932 trace_gt64120_read_intreg("INTRCAUSE", size, val); 933 break; 934 case GT_INTRMASK: 935 val = s->regs[saddr]; 936 trace_gt64120_read_intreg("INTRMASK", size, val); 937 break; 938 case GT_PCI0_ICMASK: 939 val = s->regs[saddr]; 940 trace_gt64120_read_intreg("ICMASK", size, val); 941 break; 942 case GT_PCI0_SERR0MASK: 943 val = s->regs[saddr]; 944 trace_gt64120_read_intreg("SERR0MASK", size, val); 945 break; 946 947 /* Reserved when only PCI_0 is configured. */ 948 case GT_HINTRCAUSE: 949 case GT_CPU_INTSEL: 950 case GT_PCI0_INTSEL: 951 case GT_HINTRMASK: 952 case GT_PCI0_HICMASK: 953 case GT_PCI1_SERR1MASK: 954 val = s->regs[saddr]; 955 break; 956 957 default: 958 val = s->regs[saddr]; 959 qemu_log_mask(LOG_GUEST_ERROR, 960 "gt64120: Illegal register read " 961 "reg:0x%03x size:%u value:0x%0*x\n", 962 saddr << 2, size, size << 1, val); 963 break; 964 } 965 966 if (!(s->regs[GT_CPU] & 0x00001000)) { 967 val = bswap32(val); 968 } 969 trace_gt64120_read(addr, val); 970 971 return val; 972} 973 974static const MemoryRegionOps isd_mem_ops = { 975 .read = gt64120_readl, 976 .write = gt64120_writel, 977 .endianness = DEVICE_NATIVE_ENDIAN, 978 .impl = { 979 .min_access_size = 4, 980 .max_access_size = 4, 981 }, 982}; 983 984static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) 985{ 986 int slot; 987 988 slot = PCI_SLOT(pci_dev->devfn); 989 990 switch (slot) { 991 /* PIIX4 USB */ 992 case 10: 993 return 3; 994 /* AMD 79C973 Ethernet */ 995 case 11: 996 return 1; 997 /* Crystal 4281 Sound */ 998 case 12: 999 return 2; 1000 /* PCI slot 1 to 4 */ 1001 case 18 ... 21: 1002 return ((slot - 18) + irq_num) & 0x03; 1003 /* Unknown device, don't do any translation */ 1004 default: 1005 return irq_num; 1006 } 1007} 1008 1009static int pci_irq_levels[4]; 1010 1011static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) 1012{ 1013 int i, pic_irq, pic_level; 1014 qemu_irq *pic = opaque; 1015 1016 pci_irq_levels[irq_num] = level; 1017 1018 /* now we change the pic irq level according to the piix irq mappings */ 1019 /* XXX: optimize */ 1020 pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; 1021 if (pic_irq < 16) { 1022 /* The pic level is the logical OR of all the PCI irqs mapped to it. */ 1023 pic_level = 0; 1024 for (i = 0; i < 4; i++) { 1025 if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { 1026 pic_level |= pci_irq_levels[i]; 1027 } 1028 } 1029 qemu_set_irq(pic[pic_irq], pic_level); 1030 } 1031} 1032 1033 1034static void gt64120_reset(DeviceState *dev) 1035{ 1036 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); 1037 1038 /* FIXME: Malta specific hw assumptions ahead */ 1039 1040 /* CPU Configuration */ 1041#ifdef TARGET_WORDS_BIGENDIAN 1042 s->regs[GT_CPU] = 0x00000000; 1043#else 1044 s->regs[GT_CPU] = 0x00001000; 1045#endif 1046 s->regs[GT_MULTI] = 0x00000003; 1047 1048 /* CPU Address decode */ 1049 s->regs[GT_SCS10LD] = 0x00000000; 1050 s->regs[GT_SCS10HD] = 0x00000007; 1051 s->regs[GT_SCS32LD] = 0x00000008; 1052 s->regs[GT_SCS32HD] = 0x0000000f; 1053 s->regs[GT_CS20LD] = 0x000000e0; 1054 s->regs[GT_CS20HD] = 0x00000070; 1055 s->regs[GT_CS3BOOTLD] = 0x000000f8; 1056 s->regs[GT_CS3BOOTHD] = 0x0000007f; 1057 1058 s->regs[GT_PCI0IOLD] = 0x00000080; 1059 s->regs[GT_PCI0IOHD] = 0x0000000f; 1060 s->regs[GT_PCI0M0LD] = 0x00000090; 1061 s->regs[GT_PCI0M0HD] = 0x0000001f; 1062 s->regs[GT_ISD] = 0x000000a0; 1063 s->regs[GT_PCI0M1LD] = 0x00000790; 1064 s->regs[GT_PCI0M1HD] = 0x0000001f; 1065 s->regs[GT_PCI1IOLD] = 0x00000100; 1066 s->regs[GT_PCI1IOHD] = 0x0000000f; 1067 s->regs[GT_PCI1M0LD] = 0x00000110; 1068 s->regs[GT_PCI1M0HD] = 0x0000001f; 1069 s->regs[GT_PCI1M1LD] = 0x00000120; 1070 s->regs[GT_PCI1M1HD] = 0x0000002f; 1071 1072 s->regs[GT_SCS10AR] = 0x00000000; 1073 s->regs[GT_SCS32AR] = 0x00000008; 1074 s->regs[GT_CS20R] = 0x000000e0; 1075 s->regs[GT_CS3BOOTR] = 0x000000f8; 1076 1077 s->regs[GT_PCI0IOREMAP] = 0x00000080; 1078 s->regs[GT_PCI0M0REMAP] = 0x00000090; 1079 s->regs[GT_PCI0M1REMAP] = 0x00000790; 1080 s->regs[GT_PCI1IOREMAP] = 0x00000100; 1081 s->regs[GT_PCI1M0REMAP] = 0x00000110; 1082 s->regs[GT_PCI1M1REMAP] = 0x00000120; 1083 1084 /* CPU Error Report */ 1085 s->regs[GT_CPUERR_ADDRLO] = 0x00000000; 1086 s->regs[GT_CPUERR_ADDRHI] = 0x00000000; 1087 s->regs[GT_CPUERR_DATALO] = 0xffffffff; 1088 s->regs[GT_CPUERR_DATAHI] = 0xffffffff; 1089 s->regs[GT_CPUERR_PARITY] = 0x000000ff; 1090 1091 /* CPU Sync Barrier */ 1092 s->regs[GT_PCI0SYNC] = 0x00000000; 1093 s->regs[GT_PCI1SYNC] = 0x00000000; 1094 1095 /* SDRAM and Device Address Decode */ 1096 s->regs[GT_SCS0LD] = 0x00000000; 1097 s->regs[GT_SCS0HD] = 0x00000007; 1098 s->regs[GT_SCS1LD] = 0x00000008; 1099 s->regs[GT_SCS1HD] = 0x0000000f; 1100 s->regs[GT_SCS2LD] = 0x00000010; 1101 s->regs[GT_SCS2HD] = 0x00000017; 1102 s->regs[GT_SCS3LD] = 0x00000018; 1103 s->regs[GT_SCS3HD] = 0x0000001f; 1104 s->regs[GT_CS0LD] = 0x000000c0; 1105 s->regs[GT_CS0HD] = 0x000000c7; 1106 s->regs[GT_CS1LD] = 0x000000c8; 1107 s->regs[GT_CS1HD] = 0x000000cf; 1108 s->regs[GT_CS2LD] = 0x000000d0; 1109 s->regs[GT_CS2HD] = 0x000000df; 1110 s->regs[GT_CS3LD] = 0x000000f0; 1111 s->regs[GT_CS3HD] = 0x000000fb; 1112 s->regs[GT_BOOTLD] = 0x000000fc; 1113 s->regs[GT_BOOTHD] = 0x000000ff; 1114 s->regs[GT_ADERR] = 0xffffffff; 1115 1116 /* SDRAM Configuration */ 1117 s->regs[GT_SDRAM_CFG] = 0x00000200; 1118 s->regs[GT_SDRAM_OPMODE] = 0x00000000; 1119 s->regs[GT_SDRAM_BM] = 0x00000007; 1120 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; 1121 1122 /* SDRAM Parameters */ 1123 s->regs[GT_SDRAM_B0] = 0x00000005; 1124 s->regs[GT_SDRAM_B1] = 0x00000005; 1125 s->regs[GT_SDRAM_B2] = 0x00000005; 1126 s->regs[GT_SDRAM_B3] = 0x00000005; 1127 1128 /* ECC */ 1129 s->regs[GT_ECC_ERRDATALO] = 0x00000000; 1130 s->regs[GT_ECC_ERRDATAHI] = 0x00000000; 1131 s->regs[GT_ECC_MEM] = 0x00000000; 1132 s->regs[GT_ECC_CALC] = 0x00000000; 1133 s->regs[GT_ECC_ERRADDR] = 0x00000000; 1134 1135 /* Device Parameters */ 1136 s->regs[GT_DEV_B0] = 0x386fffff; 1137 s->regs[GT_DEV_B1] = 0x386fffff; 1138 s->regs[GT_DEV_B2] = 0x386fffff; 1139 s->regs[GT_DEV_B3] = 0x386fffff; 1140 s->regs[GT_DEV_BOOT] = 0x146fffff; 1141 1142 /* DMA registers are all zeroed at reset */ 1143 1144 /* Timer/Counter */ 1145 s->regs[GT_TC0] = 0xffffffff; 1146 s->regs[GT_TC1] = 0x00ffffff; 1147 s->regs[GT_TC2] = 0x00ffffff; 1148 s->regs[GT_TC3] = 0x00ffffff; 1149 s->regs[GT_TC_CONTROL] = 0x00000000; 1150 1151 /* PCI Internal */ 1152#ifdef TARGET_WORDS_BIGENDIAN 1153 s->regs[GT_PCI0_CMD] = 0x00000000; 1154#else 1155 s->regs[GT_PCI0_CMD] = 0x00010001; 1156#endif 1157 s->regs[GT_PCI0_TOR] = 0x0000070f; 1158 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; 1159 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; 1160 s->regs[GT_PCI0_BS_CS20] = 0x01fff000; 1161 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; 1162 s->regs[GT_PCI1_IACK] = 0x00000000; 1163 s->regs[GT_PCI0_IACK] = 0x00000000; 1164 s->regs[GT_PCI0_BARE] = 0x0000000f; 1165 s->regs[GT_PCI0_PREFMBR] = 0x00000040; 1166 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; 1167 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; 1168 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; 1169 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; 1170 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; 1171 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; 1172 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; 1173#ifdef TARGET_WORDS_BIGENDIAN 1174 s->regs[GT_PCI1_CMD] = 0x00000000; 1175#else 1176 s->regs[GT_PCI1_CMD] = 0x00010001; 1177#endif 1178 s->regs[GT_PCI1_TOR] = 0x0000070f; 1179 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; 1180 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; 1181 s->regs[GT_PCI1_BS_CS20] = 0x01fff000; 1182 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; 1183 s->regs[GT_PCI1_BARE] = 0x0000000f; 1184 s->regs[GT_PCI1_PREFMBR] = 0x00000040; 1185 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; 1186 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; 1187 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; 1188 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; 1189 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; 1190 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; 1191 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; 1192 s->regs[GT_PCI1_CFGADDR] = 0x00000000; 1193 s->regs[GT_PCI1_CFGDATA] = 0x00000000; 1194 s->regs[GT_PCI0_CFGADDR] = 0x00000000; 1195 1196 /* Interrupt registers are all zeroed at reset */ 1197 1198 gt64120_isd_mapping(s); 1199 gt64120_pci_mapping(s); 1200} 1201 1202static void gt64120_realize(DeviceState *dev, Error **errp) 1203{ 1204 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); 1205 1206 memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s, 1207 "gt64120-isd", 0x1000); 1208} 1209 1210PCIBus *gt64120_register(qemu_irq *pic) 1211{ 1212 GT64120State *d; 1213 PCIHostState *phb; 1214 DeviceState *dev; 1215 1216 dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE); 1217 d = GT64120_PCI_HOST_BRIDGE(dev); 1218 phb = PCI_HOST_BRIDGE(dev); 1219 memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); 1220 address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); 1221 phb->bus = pci_register_root_bus(dev, "pci", 1222 gt64120_pci_set_irq, gt64120_pci_map_irq, 1223 pic, 1224 &d->pci0_mem, 1225 get_system_io(), 1226 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); 1227 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1228 1229 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); 1230 return phb->bus; 1231} 1232 1233static void gt64120_pci_realize(PCIDevice *d, Error **errp) 1234{ 1235 /* FIXME: Malta specific hw assumptions ahead */ 1236 pci_set_word(d->config + PCI_COMMAND, 0); 1237 pci_set_word(d->config + PCI_STATUS, 1238 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 1239 pci_config_set_prog_interface(d->config, 0); 1240 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008); 1241 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008); 1242 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000); 1243 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000); 1244 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); 1245 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); 1246 pci_set_byte(d->config + 0x3d, 0x01); 1247} 1248 1249static void gt64120_pci_class_init(ObjectClass *klass, void *data) 1250{ 1251 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1252 DeviceClass *dc = DEVICE_CLASS(klass); 1253 1254 k->realize = gt64120_pci_realize; 1255 k->vendor_id = PCI_VENDOR_ID_MARVELL; 1256 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; 1257 k->revision = 0x10; 1258 k->class_id = PCI_CLASS_BRIDGE_HOST; 1259 /* 1260 * PCI-facing part of the host bridge, not usable without the 1261 * host-facing part, which can't be device_add'ed, yet. 1262 */ 1263 dc->user_creatable = false; 1264} 1265 1266static const TypeInfo gt64120_pci_info = { 1267 .name = "gt64120_pci", 1268 .parent = TYPE_PCI_DEVICE, 1269 .instance_size = sizeof(PCIDevice), 1270 .class_init = gt64120_pci_class_init, 1271 .interfaces = (InterfaceInfo[]) { 1272 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1273 { }, 1274 }, 1275}; 1276 1277static void gt64120_class_init(ObjectClass *klass, void *data) 1278{ 1279 DeviceClass *dc = DEVICE_CLASS(klass); 1280 1281 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1282 dc->realize = gt64120_realize; 1283 dc->reset = gt64120_reset; 1284 dc->vmsd = &vmstate_gt64120; 1285} 1286 1287static const TypeInfo gt64120_info = { 1288 .name = TYPE_GT64120_PCI_HOST_BRIDGE, 1289 .parent = TYPE_PCI_HOST_BRIDGE, 1290 .instance_size = sizeof(GT64120State), 1291 .class_init = gt64120_class_init, 1292}; 1293 1294static void gt64120_pci_register_types(void) 1295{ 1296 type_register_static(>64120_info); 1297 type_register_static(>64120_pci_info); 1298} 1299 1300type_init(gt64120_pci_register_types)