cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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omap_tap.c (3545B)

      1/*
      2 * TI OMAP TEST-Chip-level TAP emulation.
      3 *
      4 * Copyright (C) 2007-2008 Nokia Corporation
      5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
      6 *
      7 * This program is free software; you can redistribute it and/or
      8 * modify it under the terms of the GNU General Public License as
      9 * published by the Free Software Foundation; either version 2 or
     10 * (at your option) any later version of the License.
     11 *
     12 * This program is distributed in the hope that it will be useful,
     13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15 * GNU General Public License for more details.
     16 *
     17 * You should have received a copy of the GNU General Public License along
     18 * with this program; if not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#include "qemu/osdep.h"
     22#include "hw/hw.h"
     23#include "hw/arm/omap.h"
     24
     25/* TEST-Chip-level TAP */
     26static uint64_t omap_tap_read(void *opaque, hwaddr addr,
     27                              unsigned size)
     28{
     29    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
     30
     31    if (size != 4) {
     32        return omap_badwidth_read32(opaque, addr);
     33    }
     34
     35    switch (addr) {
     36    case 0x204:	/* IDCODE_reg */
     37        switch (s->mpu_model) {
     38        case omap2420:
     39        case omap2422:
     40        case omap2423:
     41            return 0x5b5d902f;	/* ES 2.2 */
     42        case omap2430:
     43            return 0x5b68a02f;	/* ES 2.2 */
     44        case omap3430:
     45            return 0x1b7ae02f;	/* ES 2 */
     46        default:
     47            hw_error("%s: Bad mpu model\n", __func__);
     48        }
     49
     50    case 0x208:	/* PRODUCTION_ID_reg for OMAP2 */
     51    case 0x210:	/* PRODUCTION_ID_reg for OMAP3 */
     52        switch (s->mpu_model) {
     53        case omap2420:
     54            return 0x000254f0;	/* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
     55        case omap2422:
     56            return 0x000400f0;
     57        case omap2423:
     58            return 0x000800f0;
     59        case omap2430:
     60            return 0x000000f0;
     61        case omap3430:
     62            return 0x000000f0;
     63        default:
     64            hw_error("%s: Bad mpu model\n", __func__);
     65        }
     66
     67    case 0x20c:
     68        switch (s->mpu_model) {
     69        case omap2420:
     70        case omap2422:
     71        case omap2423:
     72            return 0xcafeb5d9;	/* ES 2.2 */
     73        case omap2430:
     74            return 0xcafeb68a;	/* ES 2.2 */
     75        case omap3430:
     76            return 0xcafeb7ae;	/* ES 2 */
     77        default:
     78            hw_error("%s: Bad mpu model\n", __func__);
     79        }
     80
     81    case 0x218:	/* DIE_ID_reg */
     82        return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
     83    case 0x21c:	/* DIE_ID_reg */
     84        return 0x54 << 24;
     85    case 0x220:	/* DIE_ID_reg */
     86        return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
     87    case 0x224:	/* DIE_ID_reg */
     88        return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
     89    }
     90
     91    OMAP_BAD_REG(addr);
     92    return 0;
     93}
     94
     95static void omap_tap_write(void *opaque, hwaddr addr,
     96                           uint64_t value, unsigned size)
     97{
     98    if (size != 4) {
     99        omap_badwidth_write32(opaque, addr, value);
    100        return;
    101    }
    102
    103    OMAP_BAD_REG(addr);
    104}
    105
    106static const MemoryRegionOps omap_tap_ops = {
    107    .read = omap_tap_read,
    108    .write = omap_tap_write,
    109    .endianness = DEVICE_NATIVE_ENDIAN,
    110};
    111
    112void omap_tap_init(struct omap_target_agent_s *ta,
    113                struct omap_mpu_state_s *mpu)
    114{
    115    memory_region_init_io(&mpu->tap_iomem, NULL, &omap_tap_ops, mpu, "omap.tap",
    116                          omap_l4_region_size(ta, 0));
    117    omap_l4_attach(ta, 0, &mpu->tap_iomem);
    118}