cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

vmxnet3_defs.h (3480B)

      1/*
      2 * QEMU VMWARE VMXNET3 paravirtual NIC
      3 *
      4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
      5 *
      6 * Developed by Daynix Computing LTD (http://www.daynix.com)
      7 *
      8 * Authors:
      9 * Dmitry Fleytman <dmitry@daynix.com>
     10 * Tamir Shomer <tamirs@daynix.com>
     11 * Yan Vugenfirer <yan@daynix.com>
     12 *
     13 * This work is licensed under the terms of the GNU GPL, version 2.
     14 * See the COPYING file in the top-level directory.
     15 */
     16
     17#ifndef HW_NET_VMXNET3_DEFS_H
     18#define HW_NET_VMXNET3_DEFS_H
     19
     20#include "net/net.h"
     21#include "hw/net/vmxnet3.h"
     22#include "qom/object.h"
     23
     24#define TYPE_VMXNET3 "vmxnet3"
     25typedef struct VMXNET3State VMXNET3State;
     26DECLARE_INSTANCE_CHECKER(VMXNET3State, VMXNET3,
     27                         TYPE_VMXNET3)
     28
     29/* Device state and helper functions */
     30#define VMXNET3_RX_RINGS_PER_QUEUE (2)
     31
     32/* Cyclic ring abstraction */
     33typedef struct {
     34    hwaddr pa;
     35    uint32_t size;
     36    uint32_t cell_size;
     37    uint32_t next;
     38    uint8_t gen;
     39} Vmxnet3Ring;
     40
     41typedef struct {
     42    Vmxnet3Ring tx_ring;
     43    Vmxnet3Ring comp_ring;
     44
     45    uint8_t intr_idx;
     46    hwaddr tx_stats_pa;
     47    struct UPT1_TxStats txq_stats;
     48} Vmxnet3TxqDescr;
     49
     50typedef struct {
     51    Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
     52    Vmxnet3Ring comp_ring;
     53    uint8_t intr_idx;
     54    hwaddr rx_stats_pa;
     55    struct UPT1_RxStats rxq_stats;
     56} Vmxnet3RxqDescr;
     57
     58typedef struct {
     59    bool is_masked;
     60    bool is_pending;
     61    bool is_asserted;
     62} Vmxnet3IntState;
     63
     64struct VMXNET3State {
     65        PCIDevice parent_obj;
     66        NICState *nic;
     67        NICConf conf;
     68        MemoryRegion bar0;
     69        MemoryRegion bar1;
     70        MemoryRegion msix_bar;
     71
     72        Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
     73        Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
     74
     75        /* Whether MSI-X support was installed successfully */
     76        bool msix_used;
     77        hwaddr drv_shmem;
     78        hwaddr temp_shared_guest_driver_memory;
     79
     80        uint8_t txq_num;
     81
     82        /* This boolean tells whether RX packet being indicated has to */
     83        /* be split into head and body chunks from different RX rings  */
     84        bool rx_packets_compound;
     85
     86        bool rx_vlan_stripping;
     87        bool lro_supported;
     88
     89        uint8_t rxq_num;
     90
     91        /* Network MTU */
     92        uint32_t mtu;
     93
     94        /* Maximum number of fragments for indicated TX packets */
     95        uint32_t max_tx_frags;
     96
     97        /* Maximum number of fragments for indicated RX packets */
     98        uint16_t max_rx_frags;
     99
    100        /* Index for events interrupt */
    101        uint8_t event_int_idx;
    102
    103        /* Whether automatic interrupts masking enabled */
    104        bool auto_int_masking;
    105
    106        bool peer_has_vhdr;
    107
    108        /* TX packets to QEMU interface */
    109        struct NetTxPkt *tx_pkt;
    110        uint32_t offload_mode;
    111        uint32_t cso_or_gso_size;
    112        uint16_t tci;
    113        bool needs_vlan;
    114
    115        struct NetRxPkt *rx_pkt;
    116
    117        bool tx_sop;
    118        bool skip_current_tx_pkt;
    119
    120        uint32_t device_active;
    121        uint32_t last_command;
    122
    123        uint32_t link_status_and_speed;
    124
    125        Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
    126
    127        uint32_t temp_mac;   /* To store the low part first */
    128
    129        MACAddr perm_mac;
    130        uint32_t vlan_table[VMXNET3_VFT_SIZE];
    131        uint32_t rx_mode;
    132        MACAddr *mcast_list;
    133        uint32_t mcast_list_len;
    134        uint32_t mcast_list_buff_size; /* needed for live migration. */
    135
    136        /* Compatibility flags for migration */
    137        uint32_t compat_flags;
    138};
    139
    140#endif