xilinx_axienet.c (29018B)
1/* 2 * QEMU model of Xilinx AXI-Ethernet. 3 * 4 * Copyright (c) 2011 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "qemu/osdep.h" 26#include "hw/hw.h" 27#include "hw/sysbus.h" 28#include "qapi/error.h" 29#include "qemu/log.h" 30#include "qemu/module.h" 31#include "net/net.h" 32#include "net/checksum.h" 33 34#include "hw/hw.h" 35#include "hw/irq.h" 36#include "hw/qdev-properties.h" 37#include "hw/stream.h" 38#include "qom/object.h" 39 40#define DPHY(x) 41 42#define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet" 43#define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream" 44#define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream" 45 46OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET) 47 48typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink; 49DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_DATA_STREAM, 50 TYPE_XILINX_AXI_ENET_DATA_STREAM) 51 52DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_CONTROL_STREAM, 53 TYPE_XILINX_AXI_ENET_CONTROL_STREAM) 54 55/* Advertisement control register. */ 56#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 57#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 58#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 59 60#define CONTROL_PAYLOAD_WORDS 5 61#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) 62 63struct PHY { 64 uint32_t regs[32]; 65 66 int link; 67 68 unsigned int (*read)(struct PHY *phy, unsigned int req); 69 void (*write)(struct PHY *phy, unsigned int req, 70 unsigned int data); 71}; 72 73static unsigned int tdk_read(struct PHY *phy, unsigned int req) 74{ 75 int regnum; 76 unsigned r = 0; 77 78 regnum = req & 0x1f; 79 80 switch (regnum) { 81 case 1: 82 if (!phy->link) { 83 break; 84 } 85 /* MR1. */ 86 /* Speeds and modes. */ 87 r |= (1 << 13) | (1 << 14); 88 r |= (1 << 11) | (1 << 12); 89 r |= (1 << 5); /* Autoneg complete. */ 90 r |= (1 << 3); /* Autoneg able. */ 91 r |= (1 << 2); /* link. */ 92 r |= (1 << 1); /* link. */ 93 break; 94 case 5: 95 /* Link partner ability. 96 We are kind; always agree with whatever best mode 97 the guest advertises. */ 98 r = 1 << 14; /* Success. */ 99 /* Copy advertised modes. */ 100 r |= phy->regs[4] & (15 << 5); 101 /* Autoneg support. */ 102 r |= 1; 103 break; 104 case 17: 105 /* Marvell PHY on many xilinx boards. */ 106 r = 0x8000; /* 1000Mb */ 107 break; 108 case 18: 109 { 110 /* Diagnostics reg. */ 111 int duplex = 0; 112 int speed_100 = 0; 113 114 if (!phy->link) { 115 break; 116 } 117 118 /* Are we advertising 100 half or 100 duplex ? */ 119 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 120 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 121 122 /* Are we advertising 10 duplex or 100 duplex ? */ 123 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 124 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 125 r = (speed_100 << 10) | (duplex << 11); 126 } 127 break; 128 129 default: 130 r = phy->regs[regnum]; 131 break; 132 } 133 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 134 return r; 135} 136 137static void 138tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 139{ 140 int regnum; 141 142 regnum = req & 0x1f; 143 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 144 switch (regnum) { 145 default: 146 phy->regs[regnum] = data; 147 break; 148 } 149 150 /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */ 151 phy->regs[0] &= ~0x8200; 152} 153 154static void 155tdk_init(struct PHY *phy) 156{ 157 phy->regs[0] = 0x3100; 158 /* PHY Id. */ 159 phy->regs[2] = 0x0300; 160 phy->regs[3] = 0xe400; 161 /* Autonegotiation advertisement reg. */ 162 phy->regs[4] = 0x01E1; 163 phy->link = 1; 164 165 phy->read = tdk_read; 166 phy->write = tdk_write; 167} 168 169struct MDIOBus { 170 struct PHY *devs[32]; 171}; 172 173static void 174mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 175{ 176 bus->devs[addr & 0x1f] = phy; 177} 178 179#ifdef USE_THIS_DEAD_CODE 180static void 181mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 182{ 183 bus->devs[addr & 0x1f] = NULL; 184} 185#endif 186 187static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 188 unsigned int reg) 189{ 190 struct PHY *phy; 191 uint16_t data; 192 193 phy = bus->devs[addr]; 194 if (phy && phy->read) { 195 data = phy->read(phy, reg); 196 } else { 197 data = 0xffff; 198 } 199 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 200 return data; 201} 202 203static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 204 unsigned int reg, uint16_t data) 205{ 206 struct PHY *phy; 207 208 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 209 phy = bus->devs[addr]; 210 if (phy && phy->write) { 211 phy->write(phy, reg, data); 212 } 213} 214 215#define DENET(x) 216 217#define R_RAF (0x000 / 4) 218enum { 219 RAF_MCAST_REJ = (1 << 1), 220 RAF_BCAST_REJ = (1 << 2), 221 RAF_EMCF_EN = (1 << 12), 222 RAF_NEWFUNC_EN = (1 << 11) 223}; 224 225#define R_IS (0x00C / 4) 226enum { 227 IS_HARD_ACCESS_COMPLETE = 1, 228 IS_AUTONEG = (1 << 1), 229 IS_RX_COMPLETE = (1 << 2), 230 IS_RX_REJECT = (1 << 3), 231 IS_TX_COMPLETE = (1 << 5), 232 IS_RX_DCM_LOCK = (1 << 6), 233 IS_MGM_RDY = (1 << 7), 234 IS_PHY_RST_DONE = (1 << 8), 235}; 236 237#define R_IP (0x010 / 4) 238#define R_IE (0x014 / 4) 239#define R_UAWL (0x020 / 4) 240#define R_UAWU (0x024 / 4) 241#define R_PPST (0x030 / 4) 242enum { 243 PPST_LINKSTATUS = (1 << 0), 244 PPST_PHY_LINKSTATUS = (1 << 7), 245}; 246 247#define R_STATS_RX_BYTESL (0x200 / 4) 248#define R_STATS_RX_BYTESH (0x204 / 4) 249#define R_STATS_TX_BYTESL (0x208 / 4) 250#define R_STATS_TX_BYTESH (0x20C / 4) 251#define R_STATS_RXL (0x290 / 4) 252#define R_STATS_RXH (0x294 / 4) 253#define R_STATS_RX_BCASTL (0x2a0 / 4) 254#define R_STATS_RX_BCASTH (0x2a4 / 4) 255#define R_STATS_RX_MCASTL (0x2a8 / 4) 256#define R_STATS_RX_MCASTH (0x2ac / 4) 257 258#define R_RCW0 (0x400 / 4) 259#define R_RCW1 (0x404 / 4) 260enum { 261 RCW1_VLAN = (1 << 27), 262 RCW1_RX = (1 << 28), 263 RCW1_FCS = (1 << 29), 264 RCW1_JUM = (1 << 30), 265 RCW1_RST = (1 << 31), 266}; 267 268#define R_TC (0x408 / 4) 269enum { 270 TC_VLAN = (1 << 27), 271 TC_TX = (1 << 28), 272 TC_FCS = (1 << 29), 273 TC_JUM = (1 << 30), 274 TC_RST = (1 << 31), 275}; 276 277#define R_EMMC (0x410 / 4) 278enum { 279 EMMC_LINKSPEED_10MB = (0 << 30), 280 EMMC_LINKSPEED_100MB = (1 << 30), 281 EMMC_LINKSPEED_1000MB = (2 << 30), 282}; 283 284#define R_PHYC (0x414 / 4) 285 286#define R_MC (0x500 / 4) 287#define MC_EN (1 << 6) 288 289#define R_MCR (0x504 / 4) 290#define R_MWD (0x508 / 4) 291#define R_MRD (0x50c / 4) 292#define R_MIS (0x600 / 4) 293#define R_MIP (0x620 / 4) 294#define R_MIE (0x640 / 4) 295#define R_MIC (0x640 / 4) 296 297#define R_UAW0 (0x700 / 4) 298#define R_UAW1 (0x704 / 4) 299#define R_FMI (0x708 / 4) 300#define R_AF0 (0x710 / 4) 301#define R_AF1 (0x714 / 4) 302#define R_MAX (0x34 / 4) 303 304/* Indirect registers. */ 305struct TEMAC { 306 struct MDIOBus mdio_bus; 307 struct PHY phy; 308 309 void *parent; 310}; 311 312 313struct XilinxAXIEnetStreamSink { 314 Object parent; 315 316 struct XilinxAXIEnet *enet; 317} ; 318 319struct XilinxAXIEnet { 320 SysBusDevice busdev; 321 MemoryRegion iomem; 322 qemu_irq irq; 323 StreamSink *tx_data_dev; 324 StreamSink *tx_control_dev; 325 XilinxAXIEnetStreamSink rx_data_dev; 326 XilinxAXIEnetStreamSink rx_control_dev; 327 NICState *nic; 328 NICConf conf; 329 330 331 uint32_t c_rxmem; 332 uint32_t c_txmem; 333 uint32_t c_phyaddr; 334 335 struct TEMAC TEMAC; 336 337 /* MII regs. */ 338 union { 339 uint32_t regs[4]; 340 struct { 341 uint32_t mc; 342 uint32_t mcr; 343 uint32_t mwd; 344 uint32_t mrd; 345 }; 346 } mii; 347 348 struct { 349 uint64_t rx_bytes; 350 uint64_t tx_bytes; 351 352 uint64_t rx; 353 uint64_t rx_bcast; 354 uint64_t rx_mcast; 355 } stats; 356 357 /* Receive configuration words. */ 358 uint32_t rcw[2]; 359 /* Transmit config. */ 360 uint32_t tc; 361 uint32_t emmc; 362 uint32_t phyc; 363 364 /* Unicast Address Word. */ 365 uint32_t uaw[2]; 366 /* Unicast address filter used with extended mcast. */ 367 uint32_t ext_uaw[2]; 368 uint32_t fmi; 369 370 uint32_t regs[R_MAX]; 371 372 /* Multicast filter addrs. */ 373 uint32_t maddr[4][2]; 374 /* 32K x 1 lookup filter. */ 375 uint32_t ext_mtable[1024]; 376 377 uint32_t hdr[CONTROL_PAYLOAD_WORDS]; 378 379 uint8_t *txmem; 380 uint32_t txpos; 381 382 uint8_t *rxmem; 383 uint32_t rxsize; 384 uint32_t rxpos; 385 386 uint8_t rxapp[CONTROL_PAYLOAD_SIZE]; 387 uint32_t rxappsize; 388 389 /* Whether axienet_eth_rx_notify should flush incoming queue. */ 390 bool need_flush; 391}; 392 393static void axienet_rx_reset(XilinxAXIEnet *s) 394{ 395 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 396} 397 398static void axienet_tx_reset(XilinxAXIEnet *s) 399{ 400 s->tc = TC_JUM | TC_TX | TC_VLAN; 401 s->txpos = 0; 402} 403 404static inline int axienet_rx_resetting(XilinxAXIEnet *s) 405{ 406 return s->rcw[1] & RCW1_RST; 407} 408 409static inline int axienet_rx_enabled(XilinxAXIEnet *s) 410{ 411 return s->rcw[1] & RCW1_RX; 412} 413 414static inline int axienet_extmcf_enabled(XilinxAXIEnet *s) 415{ 416 return !!(s->regs[R_RAF] & RAF_EMCF_EN); 417} 418 419static inline int axienet_newfunc_enabled(XilinxAXIEnet *s) 420{ 421 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 422} 423 424static void xilinx_axienet_reset(DeviceState *d) 425{ 426 XilinxAXIEnet *s = XILINX_AXI_ENET(d); 427 428 axienet_rx_reset(s); 429 axienet_tx_reset(s); 430 431 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 432 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 433 434 s->emmc = EMMC_LINKSPEED_100MB; 435} 436 437static void enet_update_irq(XilinxAXIEnet *s) 438{ 439 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 440 qemu_set_irq(s->irq, !!s->regs[R_IP]); 441} 442 443static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) 444{ 445 XilinxAXIEnet *s = opaque; 446 uint32_t r = 0; 447 addr >>= 2; 448 449 switch (addr) { 450 case R_RCW0: 451 case R_RCW1: 452 r = s->rcw[addr & 1]; 453 break; 454 455 case R_TC: 456 r = s->tc; 457 break; 458 459 case R_EMMC: 460 r = s->emmc; 461 break; 462 463 case R_PHYC: 464 r = s->phyc; 465 break; 466 467 case R_MCR: 468 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 469 break; 470 471 case R_STATS_RX_BYTESL: 472 case R_STATS_RX_BYTESH: 473 r = s->stats.rx_bytes >> (32 * (addr & 1)); 474 break; 475 476 case R_STATS_TX_BYTESL: 477 case R_STATS_TX_BYTESH: 478 r = s->stats.tx_bytes >> (32 * (addr & 1)); 479 break; 480 481 case R_STATS_RXL: 482 case R_STATS_RXH: 483 r = s->stats.rx >> (32 * (addr & 1)); 484 break; 485 case R_STATS_RX_BCASTL: 486 case R_STATS_RX_BCASTH: 487 r = s->stats.rx_bcast >> (32 * (addr & 1)); 488 break; 489 case R_STATS_RX_MCASTL: 490 case R_STATS_RX_MCASTH: 491 r = s->stats.rx_mcast >> (32 * (addr & 1)); 492 break; 493 494 case R_MC: 495 case R_MWD: 496 case R_MRD: 497 r = s->mii.regs[addr & 3]; 498 break; 499 500 case R_UAW0: 501 case R_UAW1: 502 r = s->uaw[addr & 1]; 503 break; 504 505 case R_UAWU: 506 case R_UAWL: 507 r = s->ext_uaw[addr & 1]; 508 break; 509 510 case R_FMI: 511 r = s->fmi; 512 break; 513 514 case R_AF0: 515 case R_AF1: 516 r = s->maddr[s->fmi & 3][addr & 1]; 517 break; 518 519 case 0x8000 ... 0x83ff: 520 r = s->ext_mtable[addr - 0x8000]; 521 break; 522 523 default: 524 if (addr < ARRAY_SIZE(s->regs)) { 525 r = s->regs[addr]; 526 } 527 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 528 __func__, addr * 4, r)); 529 break; 530 } 531 return r; 532} 533 534static void enet_write(void *opaque, hwaddr addr, 535 uint64_t value, unsigned size) 536{ 537 XilinxAXIEnet *s = opaque; 538 struct TEMAC *t = &s->TEMAC; 539 540 addr >>= 2; 541 switch (addr) { 542 case R_RCW0: 543 case R_RCW1: 544 s->rcw[addr & 1] = value; 545 if ((addr & 1) && value & RCW1_RST) { 546 axienet_rx_reset(s); 547 } else { 548 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 549 } 550 break; 551 552 case R_TC: 553 s->tc = value; 554 if (value & TC_RST) { 555 axienet_tx_reset(s); 556 } 557 break; 558 559 case R_EMMC: 560 s->emmc = value; 561 break; 562 563 case R_PHYC: 564 s->phyc = value; 565 break; 566 567 case R_MC: 568 value &= ((1 << 7) - 1); 569 570 /* Enable the MII. */ 571 if (value & MC_EN) { 572 unsigned int miiclkdiv = value & ((1 << 6) - 1); 573 if (!miiclkdiv) { 574 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 575 } 576 } 577 s->mii.mc = value; 578 break; 579 580 case R_MCR: { 581 unsigned int phyaddr = (value >> 24) & 0x1f; 582 unsigned int regaddr = (value >> 16) & 0x1f; 583 unsigned int op = (value >> 14) & 3; 584 unsigned int initiate = (value >> 11) & 1; 585 586 if (initiate) { 587 if (op == 1) { 588 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 589 } else if (op == 2) { 590 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 591 } else { 592 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 593 } 594 } 595 s->mii.mcr = value; 596 break; 597 } 598 599 case R_MWD: 600 case R_MRD: 601 s->mii.regs[addr & 3] = value; 602 break; 603 604 605 case R_UAW0: 606 case R_UAW1: 607 s->uaw[addr & 1] = value; 608 break; 609 610 case R_UAWL: 611 case R_UAWU: 612 s->ext_uaw[addr & 1] = value; 613 break; 614 615 case R_FMI: 616 s->fmi = value; 617 break; 618 619 case R_AF0: 620 case R_AF1: 621 s->maddr[s->fmi & 3][addr & 1] = value; 622 break; 623 624 case R_IS: 625 s->regs[addr] &= ~value; 626 break; 627 628 case 0x8000 ... 0x83ff: 629 s->ext_mtable[addr - 0x8000] = value; 630 break; 631 632 default: 633 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 634 __func__, addr * 4, (unsigned)value)); 635 if (addr < ARRAY_SIZE(s->regs)) { 636 s->regs[addr] = value; 637 } 638 break; 639 } 640 enet_update_irq(s); 641} 642 643static const MemoryRegionOps enet_ops = { 644 .read = enet_read, 645 .write = enet_write, 646 .endianness = DEVICE_LITTLE_ENDIAN, 647}; 648 649static int eth_can_rx(XilinxAXIEnet *s) 650{ 651 /* RX enabled? */ 652 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s); 653} 654 655static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 656{ 657 int match = 1; 658 659 if (memcmp(buf, &f0, 4)) { 660 match = 0; 661 } 662 663 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 664 match = 0; 665 } 666 667 return match; 668} 669 670static void axienet_eth_rx_notify(void *opaque) 671{ 672 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque); 673 674 while (s->rxappsize && stream_can_push(s->tx_control_dev, 675 axienet_eth_rx_notify, s)) { 676 size_t ret = stream_push(s->tx_control_dev, 677 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE 678 - s->rxappsize, s->rxappsize, true); 679 s->rxappsize -= ret; 680 } 681 682 while (s->rxsize && stream_can_push(s->tx_data_dev, 683 axienet_eth_rx_notify, s)) { 684 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos, 685 s->rxsize, true); 686 s->rxsize -= ret; 687 s->rxpos += ret; 688 if (!s->rxsize) { 689 s->regs[R_IS] |= IS_RX_COMPLETE; 690 if (s->need_flush) { 691 s->need_flush = false; 692 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 693 } 694 } 695 } 696 enet_update_irq(s); 697} 698 699static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 700{ 701 XilinxAXIEnet *s = qemu_get_nic_opaque(nc); 702 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 703 0xff, 0xff, 0xff}; 704 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 705 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0}; 706 int promisc = s->fmi & (1 << 31); 707 int unicast, broadcast, multicast, ip_multicast = 0; 708 uint32_t csum32; 709 uint16_t csum16; 710 int i; 711 712 DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 713 714 if (!eth_can_rx(s)) { 715 s->need_flush = true; 716 return 0; 717 } 718 719 unicast = ~buf[0] & 0x1; 720 broadcast = memcmp(buf, sa_bcast, 6) == 0; 721 multicast = !unicast && !broadcast; 722 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 723 ip_multicast = 1; 724 } 725 726 /* Jumbo or vlan sizes ? */ 727 if (!(s->rcw[1] & RCW1_JUM)) { 728 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 729 return size; 730 } 731 } 732 733 /* Basic Address filters. If you want to use the extended filters 734 you'll generally have to place the ethernet mac into promiscuous mode 735 to avoid the basic filtering from dropping most frames. */ 736 if (!promisc) { 737 if (unicast) { 738 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 739 return size; 740 } 741 } else { 742 if (broadcast) { 743 /* Broadcast. */ 744 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 745 return size; 746 } 747 } else { 748 int drop = 1; 749 750 /* Multicast. */ 751 if (s->regs[R_RAF] & RAF_MCAST_REJ) { 752 return size; 753 } 754 755 for (i = 0; i < 4; i++) { 756 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 757 drop = 0; 758 break; 759 } 760 } 761 762 if (drop) { 763 return size; 764 } 765 } 766 } 767 } 768 769 /* Extended mcast filtering enabled? */ 770 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 771 if (unicast) { 772 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 773 return size; 774 } 775 } else { 776 if (broadcast) { 777 /* Broadcast. ??? */ 778 if (s->regs[R_RAF] & RAF_BCAST_REJ) { 779 return size; 780 } 781 } else { 782 int idx, bit; 783 784 /* Multicast. */ 785 if (!memcmp(buf, sa_ipmcast, 3)) { 786 return size; 787 } 788 789 idx = (buf[4] & 0x7f) << 8; 790 idx |= buf[5]; 791 792 bit = 1 << (idx & 0x1f); 793 idx >>= 5; 794 795 if (!(s->ext_mtable[idx] & bit)) { 796 return size; 797 } 798 } 799 } 800 } 801 802 if (size < 12) { 803 s->regs[R_IS] |= IS_RX_REJECT; 804 enet_update_irq(s); 805 return -1; 806 } 807 808 if (size > (s->c_rxmem - 4)) { 809 size = s->c_rxmem - 4; 810 } 811 812 memcpy(s->rxmem, buf, size); 813 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 814 815 if (s->rcw[1] & RCW1_FCS) { 816 size += 4; /* fcs is inband. */ 817 } 818 819 app[0] = 5 << 28; 820 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 821 /* Fold it once. */ 822 csum32 = (csum32 & 0xffff) + (csum32 >> 16); 823 /* And twice to get rid of possible carries. */ 824 csum16 = (csum32 & 0xffff) + (csum32 >> 16); 825 app[3] = csum16; 826 app[4] = size & 0xffff; 827 828 s->stats.rx_bytes += size; 829 s->stats.rx++; 830 if (multicast) { 831 s->stats.rx_mcast++; 832 app[2] |= 1 | (ip_multicast << 1); 833 } else if (broadcast) { 834 s->stats.rx_bcast++; 835 app[2] |= 1 << 3; 836 } 837 838 /* Good frame. */ 839 app[2] |= 1 << 6; 840 841 s->rxsize = size; 842 s->rxpos = 0; 843 for (i = 0; i < ARRAY_SIZE(app); ++i) { 844 app[i] = cpu_to_le32(app[i]); 845 } 846 s->rxappsize = CONTROL_PAYLOAD_SIZE; 847 memcpy(s->rxapp, app, s->rxappsize); 848 axienet_eth_rx_notify(s); 849 850 enet_update_irq(s); 851 return size; 852} 853 854static size_t 855xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len, 856 bool eop) 857{ 858 int i; 859 XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); 860 XilinxAXIEnet *s = cs->enet; 861 862 assert(eop); 863 if (len != CONTROL_PAYLOAD_SIZE) { 864 hw_error("AXI Enet requires %d byte control stream payload\n", 865 (int)CONTROL_PAYLOAD_SIZE); 866 } 867 868 memcpy(s->hdr, buf, len); 869 870 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) { 871 s->hdr[i] = le32_to_cpu(s->hdr[i]); 872 } 873 return len; 874} 875 876static size_t 877xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size, 878 bool eop) 879{ 880 XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj); 881 XilinxAXIEnet *s = ds->enet; 882 883 /* TX enable ? */ 884 if (!(s->tc & TC_TX)) { 885 return size; 886 } 887 888 if (s->txpos + size > s->c_txmem) { 889 qemu_log_mask(LOG_GUEST_ERROR, "%s: Packet larger than txmem\n", 890 TYPE_XILINX_AXI_ENET); 891 s->txpos = 0; 892 return size; 893 } 894 895 if (s->txpos == 0 && eop) { 896 /* Fast path single fragment. */ 897 s->txpos = size; 898 } else { 899 memcpy(s->txmem + s->txpos, buf, size); 900 buf = s->txmem; 901 s->txpos += size; 902 903 if (!eop) { 904 return size; 905 } 906 } 907 908 /* Jumbo or vlan sizes ? */ 909 if (!(s->tc & TC_JUM)) { 910 if (s->txpos > 1518 && s->txpos <= 1522 && !(s->tc & TC_VLAN)) { 911 s->txpos = 0; 912 return size; 913 } 914 } 915 916 if (s->hdr[0] & 1) { 917 unsigned int start_off = s->hdr[1] >> 16; 918 unsigned int write_off = s->hdr[1] & 0xffff; 919 uint32_t tmp_csum; 920 uint16_t csum; 921 922 tmp_csum = net_checksum_add(s->txpos - start_off, 923 buf + start_off); 924 /* Accumulate the seed. */ 925 tmp_csum += s->hdr[2] & 0xffff; 926 927 /* Fold the 32bit partial checksum. */ 928 csum = net_checksum_finish(tmp_csum); 929 930 /* Writeback. */ 931 buf[write_off] = csum >> 8; 932 buf[write_off + 1] = csum & 0xff; 933 } 934 935 qemu_send_packet(qemu_get_queue(s->nic), buf, s->txpos); 936 937 s->stats.tx_bytes += s->txpos; 938 s->regs[R_IS] |= IS_TX_COMPLETE; 939 enet_update_irq(s); 940 941 s->txpos = 0; 942 return size; 943} 944 945static NetClientInfo net_xilinx_enet_info = { 946 .type = NET_CLIENT_DRIVER_NIC, 947 .size = sizeof(NICState), 948 .receive = eth_rx, 949}; 950 951static void xilinx_enet_realize(DeviceState *dev, Error **errp) 952{ 953 XilinxAXIEnet *s = XILINX_AXI_ENET(dev); 954 XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); 955 XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM( 956 &s->rx_control_dev); 957 958 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", 959 (Object **) &ds->enet, 960 object_property_allow_set_link, 961 OBJ_PROP_LINK_STRONG); 962 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", 963 (Object **) &cs->enet, 964 object_property_allow_set_link, 965 OBJ_PROP_LINK_STRONG); 966 object_property_set_link(OBJECT(ds), "enet", OBJECT(s), &error_abort); 967 object_property_set_link(OBJECT(cs), "enet", OBJECT(s), &error_abort); 968 969 qemu_macaddr_default_if_unset(&s->conf.macaddr); 970 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 971 object_get_typename(OBJECT(dev)), dev->id, s); 972 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 973 974 tdk_init(&s->TEMAC.phy); 975 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 976 977 s->TEMAC.parent = s; 978 979 s->rxmem = g_malloc(s->c_rxmem); 980 s->txmem = g_malloc(s->c_txmem); 981} 982 983static void xilinx_enet_init(Object *obj) 984{ 985 XilinxAXIEnet *s = XILINX_AXI_ENET(obj); 986 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 987 988 object_initialize_child(OBJECT(s), "axistream-connected-target", 989 &s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM); 990 object_initialize_child(OBJECT(s), "axistream-control-connected-target", 991 &s->rx_control_dev, 992 TYPE_XILINX_AXI_ENET_CONTROL_STREAM); 993 sysbus_init_irq(sbd, &s->irq); 994 995 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); 996 sysbus_init_mmio(sbd, &s->iomem); 997} 998 999static Property xilinx_enet_properties[] = { 1000 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7), 1001 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000), 1002 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), 1003 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), 1004 DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, 1005 tx_data_dev, TYPE_STREAM_SINK, StreamSink *), 1006 DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, 1007 tx_control_dev, TYPE_STREAM_SINK, StreamSink *), 1008 DEFINE_PROP_END_OF_LIST(), 1009}; 1010 1011static void xilinx_enet_class_init(ObjectClass *klass, void *data) 1012{ 1013 DeviceClass *dc = DEVICE_CLASS(klass); 1014 1015 dc->realize = xilinx_enet_realize; 1016 device_class_set_props(dc, xilinx_enet_properties); 1017 dc->reset = xilinx_axienet_reset; 1018} 1019 1020static void xilinx_enet_control_stream_class_init(ObjectClass *klass, 1021 void *data) 1022{ 1023 StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); 1024 1025 ssc->push = xilinx_axienet_control_stream_push; 1026} 1027 1028static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data) 1029{ 1030 StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); 1031 1032 ssc->push = xilinx_axienet_data_stream_push; 1033} 1034 1035static const TypeInfo xilinx_enet_info = { 1036 .name = TYPE_XILINX_AXI_ENET, 1037 .parent = TYPE_SYS_BUS_DEVICE, 1038 .instance_size = sizeof(XilinxAXIEnet), 1039 .class_init = xilinx_enet_class_init, 1040 .instance_init = xilinx_enet_init, 1041}; 1042 1043static const TypeInfo xilinx_enet_data_stream_info = { 1044 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM, 1045 .parent = TYPE_OBJECT, 1046 .instance_size = sizeof(XilinxAXIEnetStreamSink), 1047 .class_init = xilinx_enet_data_stream_class_init, 1048 .interfaces = (InterfaceInfo[]) { 1049 { TYPE_STREAM_SINK }, 1050 { } 1051 } 1052}; 1053 1054static const TypeInfo xilinx_enet_control_stream_info = { 1055 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, 1056 .parent = TYPE_OBJECT, 1057 .instance_size = sizeof(XilinxAXIEnetStreamSink), 1058 .class_init = xilinx_enet_control_stream_class_init, 1059 .interfaces = (InterfaceInfo[]) { 1060 { TYPE_STREAM_SINK }, 1061 { } 1062 } 1063}; 1064 1065static void xilinx_enet_register_types(void) 1066{ 1067 type_register_static(&xilinx_enet_info); 1068 type_register_static(&xilinx_enet_data_stream_info); 1069 type_register_static(&xilinx_enet_control_stream_info); 1070} 1071 1072type_init(xilinx_enet_register_types)