cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

generic_nommu.c (3704B)

      1/*
      2 * Generic simulator target with no MMU or devices.  This emulation is
      3 * compatible with the libgloss qemu-hosted.ld linker script for using
      4 * QEMU as an instruction set simulator.
      5 *
      6 * Copyright (c) 2018-2019 Mentor Graphics
      7 *
      8 * Copyright (c) 2016 Marek Vasut <marek.vasut@gmail.com>
      9 *
     10 * Based on LabX device code
     11 *
     12 * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
     13 *
     14 * This library is free software; you can redistribute it and/or
     15 * modify it under the terms of the GNU Lesser General Public
     16 * License as published by the Free Software Foundation; either
     17 * version 2.1 of the License, or (at your option) any later version.
     18 *
     19 * This library is distributed in the hope that it will be useful,
     20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     22 * Lesser General Public License for more details.
     23 *
     24 * You should have received a copy of the GNU Lesser General Public
     25 * License along with this library; if not, see
     26 * <http://www.gnu.org/licenses/lgpl-2.1.html>
     27 */
     28
     29#include "qemu/osdep.h"
     30#include "qapi/error.h"
     31#include "qemu-common.h"
     32
     33#include "hw/char/serial.h"
     34#include "hw/boards.h"
     35#include "exec/memory.h"
     36#include "exec/address-spaces.h"
     37#include "qemu/config-file.h"
     38
     39#include "boot.h"
     40
     41#define BINARY_DEVICE_TREE_FILE    "generic-nommu.dtb"
     42
     43static void nios2_generic_nommu_init(MachineState *machine)
     44{
     45    Nios2CPU *cpu;
     46    MemoryRegion *address_space_mem = get_system_memory();
     47    MemoryRegion *phys_tcm = g_new(MemoryRegion, 1);
     48    MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1);
     49    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
     50    MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1);
     51    ram_addr_t tcm_base = 0x0;
     52    ram_addr_t tcm_size = 0x1000;    /* 1 kiB, but QEMU limit is 4 kiB */
     53    ram_addr_t ram_base = 0x10000000;
     54    ram_addr_t ram_size = 0x08000000;
     55
     56    /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */
     57    memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size,
     58                           &error_abort);
     59    memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias",
     60                             phys_tcm, 0, tcm_size);
     61    memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm);
     62    memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base,
     63                                phys_tcm_alias);
     64
     65    /* Physical DRAM with alias at 0xc0000000 */
     66    memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size,
     67                           &error_abort);
     68    memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias",
     69                             phys_ram, 0, ram_size);
     70    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
     71    memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
     72                                phys_ram_alias);
     73
     74    cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
     75
     76    /* Remove MMU */
     77    cpu->mmu_present = false;
     78
     79    /* Reset vector is the first 32 bytes of RAM.  */
     80    cpu->reset_addr = ram_base;
     81
     82    /* The interrupt vector comes right after reset.  */
     83    cpu->exception_addr = ram_base + 0x20;
     84
     85    /*
     86     * The linker script does have a TLB miss memory region declared,
     87     * but this should never be used with no MMU.
     88     */
     89    cpu->fast_tlb_miss_addr = 0x7fff400;
     90
     91    nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
     92                      BINARY_DEVICE_TREE_FILE, NULL);
     93}
     94
     95static void nios2_generic_nommu_machine_init(struct MachineClass *mc)
     96{
     97    mc->desc = "Generic NOMMU Nios II design";
     98    mc->init = nios2_generic_nommu_init;
     99}
    100
    101DEFINE_MACHINE("nios2-generic-nommu", nios2_generic_nommu_machine_init);