cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

ioh3420.c (3988B)

      1/*
      2 * ioh3420.c
      3 * Intel X58 north bridge IOH
      4 * PCI Express root port device id 3420
      5 *
      6 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
      7 *                    VA Linux Systems Japan K.K.
      8 *
      9 * This program is free software; you can redistribute it and/or modify
     10 * it under the terms of the GNU General Public License as published by
     11 * the Free Software Foundation; either version 2 of the License, or
     12 * (at your option) any later version.
     13 *
     14 * This program is distributed in the hope that it will be useful,
     15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17 * GNU General Public License for more details.
     18 *
     19 * You should have received a copy of the GNU General Public License along
     20 * with this program; if not, see <http://www.gnu.org/licenses/>.
     21 */
     22
     23#include "qemu/osdep.h"
     24#include "hw/pci/pci_ids.h"
     25#include "hw/pci/msi.h"
     26#include "hw/pci/pcie.h"
     27#include "hw/pci/pcie_port.h"
     28#include "migration/vmstate.h"
     29#include "qemu/module.h"
     30
     31#define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
     32#define PCI_DEVICE_ID_IOH_REV           0x2
     33#define IOH_EP_SSVID_OFFSET             0x40
     34#define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
     35#define IOH_EP_SSVID_SSID               0
     36#define IOH_EP_MSI_OFFSET               0x60
     37#define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
     38#define IOH_EP_MSI_NR_VECTOR            2
     39#define IOH_EP_EXP_OFFSET               0x90
     40#define IOH_EP_AER_OFFSET               0x100
     41
     42/*
     43 * If two MSI vector are allocated, Advanced Error Interrupt Message Number
     44 * is 1. otherwise 0.
     45 * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
     46 */
     47static uint8_t ioh3420_aer_vector(const PCIDevice *d)
     48{
     49    switch (msi_nr_vectors_allocated(d)) {
     50    case 1:
     51        return 0;
     52    case 2:
     53        return 1;
     54    case 4:
     55    case 8:
     56    case 16:
     57    case 32:
     58    default:
     59        break;
     60    }
     61    abort();
     62    return 0;
     63}
     64
     65static int ioh3420_interrupts_init(PCIDevice *d, Error **errp)
     66{
     67    int rc;
     68
     69    rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
     70                  IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
     71                  IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
     72                  errp);
     73    if (rc < 0) {
     74        assert(rc == -ENOTSUP);
     75    }
     76
     77    return rc;
     78}
     79
     80static void ioh3420_interrupts_uninit(PCIDevice *d)
     81{
     82    msi_uninit(d);
     83}
     84
     85static const VMStateDescription vmstate_ioh3420 = {
     86    .name = "ioh-3240-express-root-port",
     87    .priority = MIG_PRI_PCI_BUS,
     88    .version_id = 1,
     89    .minimum_version_id = 1,
     90    .post_load = pcie_cap_slot_post_load,
     91    .fields = (VMStateField[]) {
     92        VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
     93        VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
     94                       PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
     95        VMSTATE_END_OF_LIST()
     96    }
     97};
     98
     99static void ioh3420_class_init(ObjectClass *klass, void *data)
    100{
    101    DeviceClass *dc = DEVICE_CLASS(klass);
    102    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    103    PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
    104
    105    k->vendor_id = PCI_VENDOR_ID_INTEL;
    106    k->device_id = PCI_DEVICE_ID_IOH_EPORT;
    107    k->revision = PCI_DEVICE_ID_IOH_REV;
    108    dc->desc = "Intel IOH device id 3420 PCIE Root Port";
    109    dc->vmsd = &vmstate_ioh3420;
    110    rpc->aer_vector = ioh3420_aer_vector;
    111    rpc->interrupts_init = ioh3420_interrupts_init;
    112    rpc->interrupts_uninit = ioh3420_interrupts_uninit;
    113    rpc->exp_offset = IOH_EP_EXP_OFFSET;
    114    rpc->aer_offset = IOH_EP_AER_OFFSET;
    115    rpc->ssvid_offset = IOH_EP_SSVID_OFFSET;
    116    rpc->ssid = IOH_EP_SSVID_SSID;
    117}
    118
    119static const TypeInfo ioh3420_info = {
    120    .name          = "ioh3420",
    121    .parent        = TYPE_PCIE_ROOT_PORT,
    122    .class_init    = ioh3420_class_init,
    123};
    124
    125static void ioh3420_register_types(void)
    126{
    127    type_register_static(&ioh3420_info);
    128}
    129
    130type_init(ioh3420_register_types)