cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

grackle.c (5780B)


      1/*
      2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
      3 *
      4 * Copyright (c) 2006-2007 Fabrice Bellard
      5 * Copyright (c) 2007 Jocelyn Mayer
      6 *
      7 * Permission is hereby granted, free of charge, to any person obtaining a copy
      8 * of this software and associated documentation files (the "Software"), to deal
      9 * in the Software without restriction, including without limitation the rights
     10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     11 * copies of the Software, and to permit persons to whom the Software is
     12 * furnished to do so, subject to the following conditions:
     13 *
     14 * The above copyright notice and this permission notice shall be included in
     15 * all copies or substantial portions of the Software.
     16 *
     17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     23 * THE SOFTWARE.
     24 */
     25
     26#include "qemu/osdep.h"
     27#include "hw/pci/pci_host.h"
     28#include "hw/ppc/mac.h"
     29#include "hw/qdev-properties.h"
     30#include "hw/pci/pci.h"
     31#include "hw/irq.h"
     32#include "qapi/error.h"
     33#include "qemu/module.h"
     34#include "trace.h"
     35#include "qom/object.h"
     36
     37OBJECT_DECLARE_SIMPLE_TYPE(GrackleState, GRACKLE_PCI_HOST_BRIDGE)
     38
     39struct GrackleState {
     40    PCIHostState parent_obj;
     41
     42    uint32_t ofw_addr;
     43    qemu_irq irqs[4];
     44    MemoryRegion pci_mmio;
     45    MemoryRegion pci_hole;
     46    MemoryRegion pci_io;
     47};
     48
     49/* Don't know if this matches real hardware, but it agrees with OHW.  */
     50static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
     51{
     52    return (irq_num + (pci_dev->devfn >> 3)) & 3;
     53}
     54
     55static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
     56{
     57    GrackleState *s = opaque;
     58
     59    trace_grackle_set_irq(irq_num, level);
     60    qemu_set_irq(s->irqs[irq_num], level);
     61}
     62
     63static void grackle_realize(DeviceState *dev, Error **errp)
     64{
     65    GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
     66    PCIHostState *phb = PCI_HOST_BRIDGE(dev);
     67
     68    phb->bus = pci_register_root_bus(dev, NULL,
     69                                     pci_grackle_set_irq,
     70                                     pci_grackle_map_irq,
     71                                     s,
     72                                     &s->pci_mmio,
     73                                     &s->pci_io,
     74                                     0, 4, TYPE_PCI_BUS);
     75
     76    pci_create_simple(phb->bus, 0, "grackle");
     77}
     78
     79static void grackle_init(Object *obj)
     80{
     81    GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj);
     82    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     83    PCIHostState *phb = PCI_HOST_BRIDGE(obj);
     84
     85    memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
     86    memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
     87                          "pci-isa-mmio", 0x00200000);
     88
     89    memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio,
     90                             0x80000000ULL, 0x7e000000ULL);
     91
     92    memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops,
     93                          DEVICE(obj), "pci-conf-idx", 0x1000);
     94    memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops,
     95                          DEVICE(obj), "pci-data-idx", 0x1000);
     96
     97    sysbus_init_mmio(sbd, &phb->conf_mem);
     98    sysbus_init_mmio(sbd, &phb->data_mem);
     99    sysbus_init_mmio(sbd, &s->pci_hole);
    100    sysbus_init_mmio(sbd, &s->pci_io);
    101
    102    qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
    103}
    104
    105static void grackle_pci_realize(PCIDevice *d, Error **errp)
    106{
    107    d->config[0x09] = 0x01;
    108}
    109
    110static void grackle_pci_class_init(ObjectClass *klass, void *data)
    111{
    112    DeviceClass *dc = DEVICE_CLASS(klass);
    113    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    114
    115    k->realize   = grackle_pci_realize;
    116    k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
    117    k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106;
    118    k->revision  = 0x00;
    119    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    120    /*
    121     * PCI-facing part of the host bridge, not usable without the
    122     * host-facing part, which can't be device_add'ed, yet.
    123     */
    124    dc->user_creatable = false;
    125}
    126
    127static const TypeInfo grackle_pci_info = {
    128    .name          = "grackle",
    129    .parent        = TYPE_PCI_DEVICE,
    130    .instance_size = sizeof(PCIDevice),
    131    .class_init = grackle_pci_class_init,
    132    .interfaces = (InterfaceInfo[]) {
    133        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
    134        { },
    135    },
    136};
    137
    138static char *grackle_ofw_unit_address(const SysBusDevice *dev)
    139{
    140    GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
    141
    142    return g_strdup_printf("%x", s->ofw_addr);
    143}
    144
    145static Property grackle_properties[] = {
    146    DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1),
    147    DEFINE_PROP_END_OF_LIST()
    148};
    149
    150static void grackle_class_init(ObjectClass *klass, void *data)
    151{
    152    DeviceClass *dc = DEVICE_CLASS(klass);
    153    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    154
    155    dc->realize = grackle_realize;
    156    device_class_set_props(dc, grackle_properties);
    157    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
    158    dc->fw_name = "pci";
    159    sbc->explicit_ofw_unit_address = grackle_ofw_unit_address;
    160}
    161
    162static const TypeInfo grackle_host_info = {
    163    .name          = TYPE_GRACKLE_PCI_HOST_BRIDGE,
    164    .parent        = TYPE_PCI_HOST_BRIDGE,
    165    .instance_size = sizeof(GrackleState),
    166    .instance_init = grackle_init,
    167    .class_init    = grackle_class_init,
    168};
    169
    170static void grackle_register_types(void)
    171{
    172    type_register_static(&grackle_pci_info);
    173    type_register_static(&grackle_host_info);
    174}
    175
    176type_init(grackle_register_types)