e500.c (39946B)
1/* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17#include "qemu/osdep.h" 18#include "qemu-common.h" 19#include "qemu/datadir.h" 20#include "qemu/units.h" 21#include "qapi/error.h" 22#include "e500.h" 23#include "e500-ccsr.h" 24#include "net/net.h" 25#include "qemu/config-file.h" 26#include "hw/char/serial.h" 27#include "hw/pci/pci.h" 28#include "sysemu/sysemu.h" 29#include "sysemu/kvm.h" 30#include "sysemu/reset.h" 31#include "sysemu/runstate.h" 32#include "kvm_ppc.h" 33#include "sysemu/device_tree.h" 34#include "hw/ppc/openpic.h" 35#include "hw/ppc/openpic_kvm.h" 36#include "hw/ppc/ppc.h" 37#include "hw/qdev-properties.h" 38#include "hw/loader.h" 39#include "elf.h" 40#include "hw/sysbus.h" 41#include "qemu/host-utils.h" 42#include "qemu/option.h" 43#include "hw/pci-host/ppce500.h" 44#include "qemu/error-report.h" 45#include "hw/platform-bus.h" 46#include "hw/net/fsl_etsec/etsec.h" 47#include "hw/i2c/i2c.h" 48#include "hw/irq.h" 49 50#define EPAPR_MAGIC (0x45504150) 51#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 52#define DTC_LOAD_PAD 0x1800000 53#define DTC_PAD_MASK 0xFFFFF 54#define DTB_MAX_SIZE (8 * MiB) 55#define INITRD_LOAD_PAD 0x2000000 56#define INITRD_PAD_MASK 0xFFFFFF 57 58#define RAM_SIZES_ALIGN (64 * MiB) 59 60/* TODO: parameterize */ 61#define MPC8544_CCSRBAR_SIZE 0x00100000ULL 62#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 63#define MPC8544_MSI_REGS_OFFSET 0x41600ULL 64#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 65#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 66#define MPC8544_PCI_REGS_OFFSET 0x8000ULL 67#define MPC8544_PCI_REGS_SIZE 0x1000ULL 68#define MPC8544_UTIL_OFFSET 0xe0000ULL 69#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 70#define MPC8544_I2C_REGS_OFFSET 0x3000ULL 71#define MPC8XXX_GPIO_IRQ 47 72#define MPC8544_I2C_IRQ 43 73#define RTC_REGS_OFFSET 0x68 74 75#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) 76 77struct boot_info 78{ 79 uint32_t dt_base; 80 uint32_t dt_size; 81 uint32_t entry; 82}; 83 84static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 85 int nr_slots, int *len) 86{ 87 int i = 0; 88 int slot; 89 int pci_irq; 90 int host_irq; 91 int last_slot = first_slot + nr_slots; 92 uint32_t *pci_map; 93 94 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 95 pci_map = g_malloc(*len); 96 97 for (slot = first_slot; slot < last_slot; slot++) { 98 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 99 pci_map[i++] = cpu_to_be32(slot << 11); 100 pci_map[i++] = cpu_to_be32(0x0); 101 pci_map[i++] = cpu_to_be32(0x0); 102 pci_map[i++] = cpu_to_be32(pci_irq + 1); 103 pci_map[i++] = cpu_to_be32(mpic); 104 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 105 pci_map[i++] = cpu_to_be32(host_irq + 1); 106 pci_map[i++] = cpu_to_be32(0x1); 107 } 108 } 109 110 assert((i * sizeof(uint32_t)) == *len); 111 112 return pci_map; 113} 114 115static void dt_serial_create(void *fdt, unsigned long long offset, 116 const char *soc, const char *mpic, 117 const char *alias, int idx, bool defcon) 118{ 119 char *ser; 120 121 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 122 qemu_fdt_add_subnode(fdt, ser); 123 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 124 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 125 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 126 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 127 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ); 128 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 129 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 130 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 131 132 if (defcon) { 133 /* 134 * "linux,stdout-path" and "stdout" properties are deprecated by linux 135 * kernel. New platforms should only use the "stdout-path" property. Set 136 * the new property and continue using older property to remain 137 * compatible with the existing firmware. 138 */ 139 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 140 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 141 } 142 g_free(ser); 143} 144 145static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 146{ 147 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 148 int irq0 = MPC8XXX_GPIO_IRQ; 149 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 150 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 151 int gpio_ph; 152 153 qemu_fdt_add_subnode(fdt, node); 154 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 155 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 156 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 157 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 158 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 159 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 160 gpio_ph = qemu_fdt_alloc_phandle(fdt); 161 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 162 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 163 164 /* Power Off Pin */ 165 qemu_fdt_add_subnode(fdt, poweroff); 166 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 167 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 168 169 g_free(node); 170 g_free(poweroff); 171} 172 173static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 174{ 175 int offset = RTC_REGS_OFFSET; 176 177 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 178 qemu_fdt_add_subnode(fdt, rtc); 179 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 180 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 181 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 182 183 g_free(rtc); 184} 185 186static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 187 const char *alias) 188{ 189 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 190 int irq0 = MPC8544_I2C_IRQ; 191 192 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 193 qemu_fdt_add_subnode(fdt, i2c); 194 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 195 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 196 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 197 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 198 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 199 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 200 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 201 202 g_free(i2c); 203} 204 205 206typedef struct PlatformDevtreeData { 207 void *fdt; 208 const char *mpic; 209 int irq_start; 210 const char *node; 211 PlatformBusDevice *pbus; 212} PlatformDevtreeData; 213 214static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 215{ 216 eTSEC *etsec = ETSEC_COMMON(sbdev); 217 PlatformBusDevice *pbus = data->pbus; 218 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 219 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 220 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 221 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 222 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 223 gchar *group = g_strdup_printf("%s/queue-group", node); 224 void *fdt = data->fdt; 225 226 assert((int64_t)mmio0 >= 0); 227 assert(irq0 >= 0); 228 assert(irq1 >= 0); 229 assert(irq2 >= 0); 230 231 qemu_fdt_add_subnode(fdt, node); 232 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0); 233 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 234 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 235 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 236 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 237 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 238 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 239 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 240 241 qemu_fdt_add_subnode(fdt, group); 242 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 243 qemu_fdt_setprop_cells(fdt, group, "interrupts", 244 data->irq_start + irq0, 0x2, 245 data->irq_start + irq1, 0x2, 246 data->irq_start + irq2, 0x2); 247 248 g_free(node); 249 g_free(group); 250 251 return 0; 252} 253 254static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 255{ 256 PlatformDevtreeData *data = opaque; 257 bool matched = false; 258 259 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 260 create_devtree_etsec(sbdev, data); 261 matched = true; 262 } 263 264 if (!matched) { 265 error_report("Device %s is not supported by this machine yet.", 266 qdev_fw_name(DEVICE(sbdev))); 267 exit(1); 268 } 269} 270 271static void platform_bus_create_devtree(PPCE500MachineState *pms, 272 void *fdt, const char *mpic) 273{ 274 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 275 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 276 const char platcomp[] = "qemu,platform\0simple-bus"; 277 uint64_t addr = pmc->platform_bus_base; 278 uint64_t size = pmc->platform_bus_size; 279 int irq_start = pmc->platform_bus_first_irq; 280 281 /* Create a /platform node that we can put all devices into */ 282 283 qemu_fdt_add_subnode(fdt, node); 284 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 285 286 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 287 address and size */ 288 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 289 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 290 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 291 292 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 293 294 /* Create dt nodes for dynamic devices */ 295 PlatformDevtreeData data = { 296 .fdt = fdt, 297 .mpic = mpic, 298 .irq_start = irq_start, 299 .node = node, 300 .pbus = pms->pbus_dev, 301 }; 302 303 /* Loop through all dynamic sysbus devices and create nodes for them */ 304 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 305 306 g_free(node); 307} 308 309static int ppce500_load_device_tree(PPCE500MachineState *pms, 310 hwaddr addr, 311 hwaddr initrd_base, 312 hwaddr initrd_size, 313 hwaddr kernel_base, 314 hwaddr kernel_size, 315 bool dry_run) 316{ 317 MachineState *machine = MACHINE(pms); 318 unsigned int smp_cpus = machine->smp.cpus; 319 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 320 CPUPPCState *env = first_cpu->env_ptr; 321 int ret = -1; 322 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 323 int fdt_size; 324 void *fdt; 325 uint8_t hypercall[16]; 326 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; 327 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; 328 int i; 329 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 330 char *soc; 331 char *mpic; 332 uint32_t mpic_ph; 333 uint32_t msi_ph; 334 char *gutil; 335 char *pci; 336 char *msi; 337 uint32_t *pci_map = NULL; 338 int len; 339 uint32_t pci_ranges[14] = 340 { 341 0x2000000, 0x0, pmc->pci_mmio_bus_base, 342 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 343 0x0, 0x20000000, 344 345 0x1000000, 0x0, 0x0, 346 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 347 0x0, 0x10000, 348 }; 349 const char *dtb_file = machine->dtb; 350 const char *toplevel_compat = machine->dt_compatible; 351 352 if (dtb_file) { 353 char *filename; 354 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 355 if (!filename) { 356 goto out; 357 } 358 359 fdt = load_device_tree(filename, &fdt_size); 360 g_free(filename); 361 if (!fdt) { 362 goto out; 363 } 364 goto done; 365 } 366 367 fdt = create_device_tree(&fdt_size); 368 if (fdt == NULL) { 369 goto out; 370 } 371 372 /* Manipulate device tree in memory. */ 373 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 374 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 375 376 qemu_fdt_add_subnode(fdt, "/memory"); 377 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 378 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 379 sizeof(mem_reg_property)); 380 381 qemu_fdt_add_subnode(fdt, "/chosen"); 382 if (initrd_size) { 383 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 384 initrd_base); 385 if (ret < 0) { 386 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 387 } 388 389 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 390 (initrd_base + initrd_size)); 391 if (ret < 0) { 392 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 393 } 394 395 } 396 397 if (kernel_base != -1ULL) { 398 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 399 kernel_base >> 32, kernel_base, 400 kernel_size >> 32, kernel_size); 401 } 402 403 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 404 machine->kernel_cmdline); 405 if (ret < 0) 406 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 407 408 if (kvm_enabled()) { 409 /* Read out host's frequencies */ 410 clock_freq = kvmppc_get_clockfreq(); 411 tb_freq = kvmppc_get_tbfreq(); 412 413 /* indicate KVM hypercall interface */ 414 qemu_fdt_add_subnode(fdt, "/hypervisor"); 415 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 416 "linux,kvm"); 417 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 418 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 419 hypercall, sizeof(hypercall)); 420 /* if KVM supports the idle hcall, set property indicating this */ 421 if (kvmppc_get_hasidle(env)) { 422 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 423 } 424 } 425 426 /* Create CPU nodes */ 427 qemu_fdt_add_subnode(fdt, "/cpus"); 428 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 429 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 430 431 /* We need to generate the cpu nodes in reverse order, so Linux can pick 432 the first node as boot node and be happy */ 433 for (i = smp_cpus - 1; i >= 0; i--) { 434 CPUState *cpu; 435 char *cpu_name; 436 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 437 438 cpu = qemu_get_cpu(i); 439 if (cpu == NULL) { 440 continue; 441 } 442 env = cpu->env_ptr; 443 444 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 445 qemu_fdt_add_subnode(fdt, cpu_name); 446 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 447 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 448 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 449 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 450 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 451 env->dcache_line_size); 452 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 453 env->icache_line_size); 454 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 455 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 456 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 457 if (cpu->cpu_index) { 458 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 459 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 460 "spin-table"); 461 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 462 cpu_release_addr); 463 } else { 464 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 465 } 466 g_free(cpu_name); 467 } 468 469 qemu_fdt_add_subnode(fdt, "/aliases"); 470 /* XXX These should go into their respective devices' code */ 471 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 472 qemu_fdt_add_subnode(fdt, soc); 473 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 474 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 475 sizeof(compatible_sb)); 476 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 477 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 478 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 479 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 480 MPC8544_CCSRBAR_SIZE); 481 /* XXX should contain a reasonable value */ 482 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 483 484 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 485 qemu_fdt_add_subnode(fdt, mpic); 486 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 487 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 488 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 489 0x40000); 490 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 491 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 492 mpic_ph = qemu_fdt_alloc_phandle(fdt); 493 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 494 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 495 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 496 497 /* 498 * We have to generate ser1 first, because Linux takes the first 499 * device it finds in the dt as serial output device. And we generate 500 * devices in reverse order to the dt. 501 */ 502 if (serial_hd(1)) { 503 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 504 soc, mpic, "serial1", 1, false); 505 } 506 507 if (serial_hd(0)) { 508 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 509 soc, mpic, "serial0", 0, true); 510 } 511 512 /* i2c */ 513 dt_i2c_create(fdt, soc, mpic, "i2c"); 514 515 dt_rtc_create(fdt, "i2c", "rtc"); 516 517 518 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 519 MPC8544_UTIL_OFFSET); 520 qemu_fdt_add_subnode(fdt, gutil); 521 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 522 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 523 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 524 g_free(gutil); 525 526 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 527 qemu_fdt_add_subnode(fdt, msi); 528 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 529 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 530 msi_ph = qemu_fdt_alloc_phandle(fdt); 531 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 532 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 533 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 534 0xe0, 0x0, 535 0xe1, 0x0, 536 0xe2, 0x0, 537 0xe3, 0x0, 538 0xe4, 0x0, 539 0xe5, 0x0, 540 0xe6, 0x0, 541 0xe7, 0x0); 542 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 543 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 544 g_free(msi); 545 546 pci = g_strdup_printf("/pci@%llx", 547 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 548 qemu_fdt_add_subnode(fdt, pci); 549 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 550 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 551 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 552 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 553 0x0, 0x7); 554 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 555 pmc->pci_first_slot, pmc->pci_nr_slots, 556 &len); 557 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 558 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 559 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 560 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 561 for (i = 0; i < 14; i++) { 562 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 563 } 564 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 565 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 566 qemu_fdt_setprop_cells(fdt, pci, "reg", 567 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 568 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 569 0, 0x1000); 570 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 571 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 572 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 573 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 574 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 575 g_free(pci); 576 577 if (pmc->has_mpc8xxx_gpio) { 578 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 579 } 580 g_free(soc); 581 582 if (pms->pbus_dev) { 583 platform_bus_create_devtree(pms, fdt, mpic); 584 } 585 g_free(mpic); 586 587 pmc->fixup_devtree(fdt); 588 589 if (toplevel_compat) { 590 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 591 strlen(toplevel_compat) + 1); 592 } 593 594done: 595 if (!dry_run) { 596 qemu_fdt_dumpdtb(fdt, fdt_size); 597 cpu_physical_memory_write(addr, fdt, fdt_size); 598 } 599 ret = fdt_size; 600 g_free(fdt); 601 602out: 603 g_free(pci_map); 604 605 return ret; 606} 607 608typedef struct DeviceTreeParams { 609 PPCE500MachineState *machine; 610 hwaddr addr; 611 hwaddr initrd_base; 612 hwaddr initrd_size; 613 hwaddr kernel_base; 614 hwaddr kernel_size; 615 Notifier notifier; 616} DeviceTreeParams; 617 618static void ppce500_reset_device_tree(void *opaque) 619{ 620 DeviceTreeParams *p = opaque; 621 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 622 p->initrd_size, p->kernel_base, p->kernel_size, 623 false); 624} 625 626static void ppce500_init_notify(Notifier *notifier, void *data) 627{ 628 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 629 ppce500_reset_device_tree(p); 630} 631 632static int ppce500_prep_device_tree(PPCE500MachineState *machine, 633 hwaddr addr, 634 hwaddr initrd_base, 635 hwaddr initrd_size, 636 hwaddr kernel_base, 637 hwaddr kernel_size) 638{ 639 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 640 p->machine = machine; 641 p->addr = addr; 642 p->initrd_base = initrd_base; 643 p->initrd_size = initrd_size; 644 p->kernel_base = kernel_base; 645 p->kernel_size = kernel_size; 646 647 qemu_register_reset(ppce500_reset_device_tree, p); 648 p->notifier.notify = ppce500_init_notify; 649 qemu_add_machine_init_done_notifier(&p->notifier); 650 651 /* Issue the device tree loader once, so that we get the size of the blob */ 652 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 653 kernel_base, kernel_size, true); 654} 655 656/* Create -kernel TLB entries for BookE. */ 657hwaddr booke206_page_size_to_tlb(uint64_t size) 658{ 659 return 63 - clz64(size / KiB); 660} 661 662static int booke206_initial_map_tsize(CPUPPCState *env) 663{ 664 struct boot_info *bi = env->load_info; 665 hwaddr dt_end; 666 int ps; 667 668 /* Our initial TLB entry needs to cover everything from 0 to 669 the device tree top */ 670 dt_end = bi->dt_base + bi->dt_size; 671 ps = booke206_page_size_to_tlb(dt_end) + 1; 672 if (ps & 1) { 673 /* e500v2 can only do even TLB size bits */ 674 ps++; 675 } 676 return ps; 677} 678 679static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 680{ 681 int tsize; 682 683 tsize = booke206_initial_map_tsize(env); 684 return (1ULL << 10 << tsize); 685} 686 687static void mmubooke_create_initial_mapping(CPUPPCState *env) 688{ 689 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 690 hwaddr size; 691 int ps; 692 693 ps = booke206_initial_map_tsize(env); 694 size = (ps << MAS1_TSIZE_SHIFT); 695 tlb->mas1 = MAS1_VALID | size; 696 tlb->mas2 = 0; 697 tlb->mas7_3 = 0; 698 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 699 700 env->tlb_dirty = true; 701} 702 703static void ppce500_cpu_reset_sec(void *opaque) 704{ 705 PowerPCCPU *cpu = opaque; 706 CPUState *cs = CPU(cpu); 707 708 cpu_reset(cs); 709 710 cs->exception_index = EXCP_HLT; 711} 712 713static void ppce500_cpu_reset(void *opaque) 714{ 715 PowerPCCPU *cpu = opaque; 716 CPUState *cs = CPU(cpu); 717 CPUPPCState *env = &cpu->env; 718 struct boot_info *bi = env->load_info; 719 720 cpu_reset(cs); 721 722 /* Set initial guest state. */ 723 cs->halted = 0; 724 env->gpr[1] = (16 * MiB) - 8; 725 env->gpr[3] = bi->dt_base; 726 env->gpr[4] = 0; 727 env->gpr[5] = 0; 728 env->gpr[6] = EPAPR_MAGIC; 729 env->gpr[7] = mmubooke_initial_mapsize(env); 730 env->gpr[8] = 0; 731 env->gpr[9] = 0; 732 env->nip = bi->entry; 733 mmubooke_create_initial_mapping(env); 734} 735 736static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 737 IrqLines *irqs) 738{ 739 DeviceState *dev; 740 SysBusDevice *s; 741 int i, j, k; 742 MachineState *machine = MACHINE(pms); 743 unsigned int smp_cpus = machine->smp.cpus; 744 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 745 746 dev = qdev_new(TYPE_OPENPIC); 747 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); 748 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 749 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 750 751 s = SYS_BUS_DEVICE(dev); 752 sysbus_realize_and_unref(s, &error_fatal); 753 754 k = 0; 755 for (i = 0; i < smp_cpus; i++) { 756 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 757 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 758 } 759 } 760 761 return dev; 762} 763 764static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 765 IrqLines *irqs, Error **errp) 766{ 767 DeviceState *dev; 768 CPUState *cs; 769 770 dev = qdev_new(TYPE_KVM_OPENPIC); 771 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 772 773 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 774 object_unparent(OBJECT(dev)); 775 return NULL; 776 } 777 778 CPU_FOREACH(cs) { 779 if (kvm_openpic_connect_vcpu(dev, cs)) { 780 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 781 __func__); 782 abort(); 783 } 784 } 785 786 return dev; 787} 788 789static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 790 MemoryRegion *ccsr, 791 IrqLines *irqs) 792{ 793 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 794 DeviceState *dev = NULL; 795 SysBusDevice *s; 796 797 if (kvm_enabled()) { 798 Error *err = NULL; 799 800 if (kvm_kernel_irqchip_allowed()) { 801 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 802 } 803 if (kvm_kernel_irqchip_required() && !dev) { 804 error_reportf_err(err, 805 "kernel_irqchip requested but unavailable: "); 806 exit(1); 807 } 808 } 809 810 if (!dev) { 811 dev = ppce500_init_mpic_qemu(pms, irqs); 812 } 813 814 s = SYS_BUS_DEVICE(dev); 815 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 816 s->mmio[0].memory); 817 818 return dev; 819} 820 821static void ppce500_power_off(void *opaque, int line, int on) 822{ 823 if (on) { 824 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 825 } 826} 827 828void ppce500_init(MachineState *machine) 829{ 830 MemoryRegion *address_space_mem = get_system_memory(); 831 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 832 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 833 PCIBus *pci_bus; 834 CPUPPCState *env = NULL; 835 uint64_t loadaddr; 836 hwaddr kernel_base = -1LL; 837 int kernel_size = 0; 838 hwaddr dt_base = 0; 839 hwaddr initrd_base = 0; 840 int initrd_size = 0; 841 hwaddr cur_base = 0; 842 char *filename; 843 const char *payload_name; 844 bool kernel_as_payload; 845 hwaddr bios_entry = 0; 846 target_long payload_size; 847 struct boot_info *boot_info; 848 int dt_size; 849 int i; 850 unsigned int smp_cpus = machine->smp.cpus; 851 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 852 * 4 respectively */ 853 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 854 IrqLines *irqs; 855 DeviceState *dev, *mpicdev; 856 CPUPPCState *firstenv = NULL; 857 MemoryRegion *ccsr_addr_space; 858 SysBusDevice *s; 859 PPCE500CCSRState *ccsr; 860 I2CBus *i2c; 861 862 irqs = g_new0(IrqLines, smp_cpus); 863 for (i = 0; i < smp_cpus; i++) { 864 PowerPCCPU *cpu; 865 CPUState *cs; 866 qemu_irq *input; 867 868 cpu = POWERPC_CPU(object_new(machine->cpu_type)); 869 env = &cpu->env; 870 cs = CPU(cpu); 871 872 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 873 error_report("MMU model %i not supported by this machine", 874 env->mmu_model); 875 exit(1); 876 } 877 878 /* 879 * Secondary CPU starts in halted state for now. Needs to change 880 * when implementing non-kernel boot. 881 */ 882 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, 883 &error_fatal); 884 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); 885 886 if (!firstenv) { 887 firstenv = env; 888 } 889 890 input = (qemu_irq *)env->irq_inputs; 891 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 892 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 893 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 894 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 895 896 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); 897 898 /* Register reset handler */ 899 if (!i) { 900 /* Primary CPU */ 901 struct boot_info *boot_info; 902 boot_info = g_malloc0(sizeof(struct boot_info)); 903 qemu_register_reset(ppce500_cpu_reset, cpu); 904 env->load_info = boot_info; 905 } else { 906 /* Secondary CPUs */ 907 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 908 } 909 } 910 911 env = firstenv; 912 913 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 914 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 915 exit(EXIT_FAILURE); 916 } 917 918 /* Register Memory */ 919 memory_region_add_subregion(address_space_mem, 0, machine->ram); 920 921 dev = qdev_new("e500-ccsr"); 922 object_property_add_child(qdev_get_machine(), "e500-ccsr", 923 OBJECT(dev)); 924 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 925 ccsr = CCSR(dev); 926 ccsr_addr_space = &ccsr->ccsr_space; 927 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 928 ccsr_addr_space); 929 930 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 931 g_free(irqs); 932 933 /* Serial */ 934 if (serial_hd(0)) { 935 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 936 0, qdev_get_gpio_in(mpicdev, 42), 399193, 937 serial_hd(0), DEVICE_BIG_ENDIAN); 938 } 939 940 if (serial_hd(1)) { 941 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 942 0, qdev_get_gpio_in(mpicdev, 42), 399193, 943 serial_hd(1), DEVICE_BIG_ENDIAN); 944 } 945 /* I2C */ 946 dev = qdev_new("mpc-i2c"); 947 s = SYS_BUS_DEVICE(dev); 948 sysbus_realize_and_unref(s, &error_fatal); 949 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 950 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 951 sysbus_mmio_get_region(s, 0)); 952 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 953 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); 954 955 956 /* General Utility device */ 957 dev = qdev_new("mpc8544-guts"); 958 s = SYS_BUS_DEVICE(dev); 959 sysbus_realize_and_unref(s, &error_fatal); 960 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 961 sysbus_mmio_get_region(s, 0)); 962 963 /* PCI */ 964 dev = qdev_new("e500-pcihost"); 965 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); 966 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 967 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 968 s = SYS_BUS_DEVICE(dev); 969 sysbus_realize_and_unref(s, &error_fatal); 970 for (i = 0; i < PCI_NUM_PINS; i++) { 971 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 972 } 973 974 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 975 sysbus_mmio_get_region(s, 0)); 976 977 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 978 if (!pci_bus) 979 printf("couldn't create PCI controller!\n"); 980 981 if (pci_bus) { 982 /* Register network interfaces. */ 983 for (i = 0; i < nb_nics; i++) { 984 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 985 } 986 } 987 988 /* Register spinning region */ 989 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 990 991 if (pmc->has_mpc8xxx_gpio) { 992 qemu_irq poweroff_irq; 993 994 dev = qdev_new("mpc8xxx_gpio"); 995 s = SYS_BUS_DEVICE(dev); 996 sysbus_realize_and_unref(s, &error_fatal); 997 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 998 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 999 sysbus_mmio_get_region(s, 0)); 1000 1001 /* Power Off GPIO at Pin 0 */ 1002 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 1003 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1004 } 1005 1006 /* Platform Bus Device */ 1007 if (pmc->has_platform_bus) { 1008 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1009 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1010 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1011 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1012 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1013 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1014 1015 s = SYS_BUS_DEVICE(pms->pbus_dev); 1016 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1017 int irqn = pmc->platform_bus_first_irq + i; 1018 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1019 } 1020 1021 memory_region_add_subregion(address_space_mem, 1022 pmc->platform_bus_base, 1023 sysbus_mmio_get_region(s, 0)); 1024 } 1025 1026 /* 1027 * Smart firmware defaults ahead! 1028 * 1029 * We follow the following table to select which payload we execute. 1030 * 1031 * -kernel | -bios | payload 1032 * ---------+-------+--------- 1033 * N | Y | u-boot 1034 * N | N | u-boot 1035 * Y | Y | u-boot 1036 * Y | N | kernel 1037 * 1038 * This ensures backwards compatibility with how we used to expose 1039 * -kernel to users but allows them to run through u-boot as well. 1040 */ 1041 kernel_as_payload = false; 1042 if (machine->firmware == NULL) { 1043 if (machine->kernel_filename) { 1044 payload_name = machine->kernel_filename; 1045 kernel_as_payload = true; 1046 } else { 1047 payload_name = "u-boot.e500"; 1048 } 1049 } else { 1050 payload_name = machine->firmware; 1051 } 1052 1053 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1054 if (!filename) { 1055 error_report("could not find firmware/kernel file '%s'", payload_name); 1056 exit(1); 1057 } 1058 1059 payload_size = load_elf(filename, NULL, NULL, NULL, 1060 &bios_entry, &loadaddr, NULL, NULL, 1061 1, PPC_ELF_MACHINE, 0, 0); 1062 if (payload_size < 0) { 1063 /* 1064 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1065 * ePAPR compliant kernel 1066 */ 1067 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1068 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1069 NULL, NULL); 1070 if (payload_size < 0) { 1071 error_report("could not load firmware '%s'", filename); 1072 exit(1); 1073 } 1074 } 1075 1076 g_free(filename); 1077 1078 if (kernel_as_payload) { 1079 kernel_base = loadaddr; 1080 kernel_size = payload_size; 1081 } 1082 1083 cur_base = loadaddr + payload_size; 1084 if (cur_base < 32 * MiB) { 1085 /* u-boot occupies memory up to 32MB, so load blobs above */ 1086 cur_base = 32 * MiB; 1087 } 1088 1089 /* Load bare kernel only if no bios/u-boot has been provided */ 1090 if (machine->kernel_filename && !kernel_as_payload) { 1091 kernel_base = cur_base; 1092 kernel_size = load_image_targphys(machine->kernel_filename, 1093 cur_base, 1094 machine->ram_size - cur_base); 1095 if (kernel_size < 0) { 1096 error_report("could not load kernel '%s'", 1097 machine->kernel_filename); 1098 exit(1); 1099 } 1100 1101 cur_base += kernel_size; 1102 } 1103 1104 /* Load initrd. */ 1105 if (machine->initrd_filename) { 1106 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1107 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1108 machine->ram_size - initrd_base); 1109 1110 if (initrd_size < 0) { 1111 error_report("could not load initial ram disk '%s'", 1112 machine->initrd_filename); 1113 exit(1); 1114 } 1115 1116 cur_base = initrd_base + initrd_size; 1117 } 1118 1119 /* 1120 * Reserve space for dtb behind the kernel image because Linux has a bug 1121 * where it can only handle the dtb if it's within the first 64MB of where 1122 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1123 * ensures enough space between kernel and initrd. 1124 */ 1125 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1126 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1127 error_report("not enough memory for device tree"); 1128 exit(1); 1129 } 1130 1131 dt_size = ppce500_prep_device_tree(pms, dt_base, 1132 initrd_base, initrd_size, 1133 kernel_base, kernel_size); 1134 if (dt_size < 0) { 1135 error_report("couldn't load device tree"); 1136 exit(1); 1137 } 1138 assert(dt_size < DTB_MAX_SIZE); 1139 1140 boot_info = env->load_info; 1141 boot_info->entry = bios_entry; 1142 boot_info->dt_base = dt_base; 1143 boot_info->dt_size = dt_size; 1144} 1145 1146static void e500_ccsr_initfn(Object *obj) 1147{ 1148 PPCE500CCSRState *ccsr = CCSR(obj); 1149 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1150 MPC8544_CCSRBAR_SIZE); 1151} 1152 1153static const TypeInfo e500_ccsr_info = { 1154 .name = TYPE_CCSR, 1155 .parent = TYPE_SYS_BUS_DEVICE, 1156 .instance_size = sizeof(PPCE500CCSRState), 1157 .instance_init = e500_ccsr_initfn, 1158}; 1159 1160static const TypeInfo ppce500_info = { 1161 .name = TYPE_PPCE500_MACHINE, 1162 .parent = TYPE_MACHINE, 1163 .abstract = true, 1164 .instance_size = sizeof(PPCE500MachineState), 1165 .class_size = sizeof(PPCE500MachineClass), 1166}; 1167 1168static void e500_register_types(void) 1169{ 1170 type_register_static(&e500_ccsr_info); 1171 type_register_static(&ppce500_info); 1172} 1173 1174type_init(e500_register_types)