cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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mpc8544_guts.c (4194B)

      1/*
      2 * QEMU PowerPC MPC8544 global util pseudo-device
      3 *
      4 * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
      5 *
      6 * Author: Alexander Graf, <alex@csgraf.de>
      7 *
      8 * This is free software; you can redistribute it and/or modify
      9 * it under the terms of  the GNU General  Public License as published by
     10 * the Free Software Foundation;  either version 2 of the  License, or
     11 * (at your option) any later version.
     12 *
     13 * *****************************************************************
     14 *
     15 * The documentation for this device is noted in the MPC8544 documentation,
     16 * file name "MPC8544ERM.pdf". You can easily find it on the web.
     17 *
     18 */
     19
     20#include "qemu/osdep.h"
     21#include "qemu/module.h"
     22#include "sysemu/runstate.h"
     23#include "cpu.h"
     24#include "hw/sysbus.h"
     25#include "qom/object.h"
     26
     27#define MPC8544_GUTS_MMIO_SIZE        0x1000
     28#define MPC8544_GUTS_RSTCR_RESET      0x02
     29
     30#define MPC8544_GUTS_ADDR_PORPLLSR    0x00
     31#define MPC8544_GUTS_ADDR_PORBMSR     0x04
     32#define MPC8544_GUTS_ADDR_PORIMPSCR   0x08
     33#define MPC8544_GUTS_ADDR_PORDEVSR    0x0C
     34#define MPC8544_GUTS_ADDR_PORDBGMSR   0x10
     35#define MPC8544_GUTS_ADDR_PORDEVSR2   0x14
     36#define MPC8544_GUTS_ADDR_GPPORCR     0x20
     37#define MPC8544_GUTS_ADDR_GPIOCR      0x30
     38#define MPC8544_GUTS_ADDR_GPOUTDR     0x40
     39#define MPC8544_GUTS_ADDR_GPINDR      0x50
     40#define MPC8544_GUTS_ADDR_PMUXCR      0x60
     41#define MPC8544_GUTS_ADDR_DEVDISR     0x70
     42#define MPC8544_GUTS_ADDR_POWMGTCSR   0x80
     43#define MPC8544_GUTS_ADDR_MCPSUMR     0x90
     44#define MPC8544_GUTS_ADDR_RSTRSCR     0x94
     45#define MPC8544_GUTS_ADDR_PVR         0xA0
     46#define MPC8544_GUTS_ADDR_SVR         0xA4
     47#define MPC8544_GUTS_ADDR_RSTCR       0xB0
     48#define MPC8544_GUTS_ADDR_IOVSELSR    0xC0
     49#define MPC8544_GUTS_ADDR_DDRCSR      0xB20
     50#define MPC8544_GUTS_ADDR_DDRCDR      0xB24
     51#define MPC8544_GUTS_ADDR_DDRCLKDR    0xB28
     52#define MPC8544_GUTS_ADDR_CLKOCR      0xE00
     53#define MPC8544_GUTS_ADDR_SRDS1CR1    0xF04
     54#define MPC8544_GUTS_ADDR_SRDS2CR1    0xF10
     55#define MPC8544_GUTS_ADDR_SRDS2CR3    0xF18
     56
     57#define TYPE_MPC8544_GUTS "mpc8544-guts"
     58OBJECT_DECLARE_SIMPLE_TYPE(GutsState, MPC8544_GUTS)
     59
     60struct GutsState {
     61    /*< private >*/
     62    SysBusDevice parent_obj;
     63    /*< public >*/
     64
     65    MemoryRegion iomem;
     66};
     67
     68
     69static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
     70                                  unsigned size)
     71{
     72    uint32_t value = 0;
     73    PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
     74    CPUPPCState *env = &cpu->env;
     75
     76    addr &= MPC8544_GUTS_MMIO_SIZE - 1;
     77    switch (addr) {
     78    case MPC8544_GUTS_ADDR_PVR:
     79        value = env->spr[SPR_PVR];
     80        break;
     81    case MPC8544_GUTS_ADDR_SVR:
     82        value = env->spr[SPR_E500_SVR];
     83        break;
     84    default:
     85        fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr);
     86        break;
     87    }
     88
     89    return value;
     90}
     91
     92static void mpc8544_guts_write(void *opaque, hwaddr addr,
     93                               uint64_t value, unsigned size)
     94{
     95    addr &= MPC8544_GUTS_MMIO_SIZE - 1;
     96
     97    switch (addr) {
     98    case MPC8544_GUTS_ADDR_RSTCR:
     99        if (value & MPC8544_GUTS_RSTCR_RESET) {
    100            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
    101        }
    102        break;
    103    default:
    104        fprintf(stderr, "guts: Unknown register write: %x = %x\n",
    105                (int)addr, (unsigned)value);
    106        break;
    107    }
    108}
    109
    110static const MemoryRegionOps mpc8544_guts_ops = {
    111    .read = mpc8544_guts_read,
    112    .write = mpc8544_guts_write,
    113    .endianness = DEVICE_BIG_ENDIAN,
    114    .valid = {
    115        .min_access_size = 4,
    116        .max_access_size = 4,
    117    },
    118};
    119
    120static void mpc8544_guts_initfn(Object *obj)
    121{
    122    SysBusDevice *d = SYS_BUS_DEVICE(obj);
    123    GutsState *s = MPC8544_GUTS(obj);
    124
    125    memory_region_init_io(&s->iomem, OBJECT(s), &mpc8544_guts_ops, s,
    126                          "mpc8544.guts", MPC8544_GUTS_MMIO_SIZE);
    127    sysbus_init_mmio(d, &s->iomem);
    128}
    129
    130static const TypeInfo mpc8544_guts_info = {
    131    .name          = TYPE_MPC8544_GUTS,
    132    .parent        = TYPE_SYS_BUS_DEVICE,
    133    .instance_size = sizeof(GutsState),
    134    .instance_init = mpc8544_guts_initfn,
    135};
    136
    137static void mpc8544_guts_register_types(void)
    138{
    139    type_register_static(&mpc8544_guts_info);
    140}
    141
    142type_init(mpc8544_guts_register_types)