cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

mpc8544ds.c (2138B)

      1/*
      2 * Support for the PPC e500-based mpc8544ds board
      3 *
      4 * Copyright 2012 Freescale Semiconductor, Inc.
      5 *
      6 * This is free software; you can redistribute it and/or modify
      7 * it under the terms of  the GNU General  Public License as published by
      8 * the Free Software Foundation;  either version 2 of the  License, or
      9 * (at your option) any later version.
     10 */
     11
     12#include "qemu/osdep.h"
     13#include "e500.h"
     14#include "sysemu/device_tree.h"
     15#include "hw/ppc/openpic.h"
     16#include "qemu/error-report.h"
     17#include "cpu.h"
     18
     19static void mpc8544ds_fixup_devtree(void *fdt)
     20{
     21    const char model[] = "MPC8544DS";
     22    const char compatible[] = "MPC8544DS\0MPC85xxDS";
     23
     24    qemu_fdt_setprop(fdt, "/", "model", model, sizeof(model));
     25    qemu_fdt_setprop(fdt, "/", "compatible", compatible,
     26                     sizeof(compatible));
     27}
     28
     29static void mpc8544ds_init(MachineState *machine)
     30{
     31    if (machine->ram_size > 0xc0000000) {
     32        error_report("The MPC8544DS board only supports up to 3GB of RAM");
     33        exit(1);
     34    }
     35
     36    ppce500_init(machine);
     37}
     38
     39static void e500plat_machine_class_init(ObjectClass *oc, void *data)
     40{
     41    MachineClass *mc = MACHINE_CLASS(oc);
     42    PPCE500MachineClass *pmc = PPCE500_MACHINE_CLASS(oc);
     43
     44    pmc->pci_first_slot = 0x11;
     45    pmc->pci_nr_slots = 2;
     46    pmc->fixup_devtree = mpc8544ds_fixup_devtree;
     47    pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
     48    pmc->ccsrbar_base = 0xE0000000ULL;
     49    pmc->pci_mmio_base = 0xC0000000ULL;
     50    pmc->pci_mmio_bus_base = 0xC0000000ULL;
     51    pmc->pci_pio_base = 0xE1000000ULL;
     52    pmc->spin_base = 0xEF000000ULL;
     53
     54    mc->desc = "mpc8544ds";
     55    mc->init = mpc8544ds_init;
     56    mc->max_cpus = 15;
     57    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30");
     58    mc->default_ram_id = "mpc8544ds.ram";
     59}
     60
     61#define TYPE_MPC8544DS_MACHINE  MACHINE_TYPE_NAME("mpc8544ds")
     62
     63static const TypeInfo mpc8544ds_info = {
     64    .name          = TYPE_MPC8544DS_MACHINE,
     65    .parent        = TYPE_PPCE500_MACHINE,
     66    .class_init    = e500plat_machine_class_init,
     67};
     68
     69static void mpc8544ds_register_types(void)
     70{
     71    type_register_static(&mpc8544ds_info);
     72}
     73
     74type_init(mpc8544ds_register_types)